1 # Copyright (c) 2016, University of Kaiserslautern
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
8 # 1. Redistributions of source code must retain the above copyright notice,
9 # this list of conditions and the following disclaimer.
11 # 2. Redistributions in binary form must reproduce the above copyright
12 # notice, this list of conditions and the following disclaimer in the
13 # documentation and/or other materials provided with the distribution.
15 # 3. Neither the name of the copyright holder nor the names of its
16 # contributors may be used to endorse or promote products derived from
17 # this software without specific prior written permission.
19 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 # TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
23 # OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 # PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
26 # PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
27 # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28 # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 # Authors: Matthias Jung
36 from m5
.objects
import *
37 from m5
.util
import addToPath
, fatal
39 addToPath('../../../configs/common/')
43 # This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU)
44 # and an external TLM port for SystemC co-simulation.
46 # We assume a DRAM size of 512MB and L1 cache sizes of 32KB.
48 # Base System Architecture:
51 # +-------------+ | eTraceCPU | |
52 # | System Port | +-----+-----+ |
53 # +------+------+ | $D1 | $I1 | |
56 # | | | | (see this file)
58 # +------v------------v-----v--+ |
60 # +----------------+-----------+ External Port (see sc_port.*)
62 # +---v---+ | TLM World
63 # | TLM | | (see sc_target.*)
67 # Create a system with a Crossbar and an Elastic Trace Player as CPU:
70 system
= System(cpu
=TraceCPU(cpu_id
=0),
72 mem_ranges
= [AddrRange('512MB')],
75 # Create a top-level voltage domain:
76 system
.voltage_domain
= VoltageDomain()
78 # Create a source clock for the system. This is used as the clock period for
80 system
.clk_domain
= SrcClockDomain(clock
= '1GHz',
81 voltage_domain
= system
.voltage_domain
)
83 # Create a CPU voltage domain:
84 system
.cpu_voltage_domain
= VoltageDomain()
86 # Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
87 # is actually used only by the caches connected to the CPU:
88 system
.cpu_clk_domain
= SrcClockDomain(clock
= '1GHz',
89 voltage_domain
= system
.cpu_voltage_domain
)
91 # Setup CPU and its L1 caches:
92 system
.cpu
.createInterruptController()
93 system
.cpu
.icache
= L1_ICache(size
="32kB")
94 system
.cpu
.dcache
= L1_DCache(size
="32kB")
95 system
.cpu
.icache
.cpu_side
= system
.cpu
.icache_port
96 system
.cpu
.dcache
.cpu_side
= system
.cpu
.dcache_port
98 # Assign input trace files to the eTraceCPU:
99 system
.cpu
.instTraceFile
="system.cpu.traceListener.inst.gz"
100 system
.cpu
.dataTraceFile
="system.cpu.traceListener.data.gz"
103 system
.membus
= IOXBar(width
= 16)
104 system
.physmem
= SimpleMemory() # This must be instantiated, even if not needed
106 # Create a external TLM port:
107 system
.tlm
= ExternalSlave()
108 system
.tlm
.addr_ranges
= [AddrRange('512MB')]
109 system
.tlm
.port_type
= "tlm_slave"
110 system
.tlm
.port_data
= "transactor"
112 # Connect everything:
113 system
.membus
= SystemXBar()
114 system
.system_port
= system
.membus
.slave
115 system
.cpu
.icache
.mem_side
= system
.membus
.slave
116 system
.cpu
.dcache
.mem_side
= system
.membus
.slave
117 system
.membus
.master
= system
.tlm
.port
119 # Start the simulation:
120 root
= Root(full_system
= False, system
= system
)
121 root
.system
.mem_mode
= 'timing'
123 m5
.simulate() #Simulation time specified later on commandline