0b017a6d11fd628c912ab1169f201aa73199aaad
2 # Copyright (c) 2016, Dresden University of Technology (TU Dresden)
5 # Redistribution and use in source and binary forms, with or without
6 # modification, are permitted provided that the following conditions are
9 # 1. Redistributions of source code must retain the above copyright notice,
10 # this list of conditions and the following disclaimer.
12 # 2. Redistributions in binary form must reproduce the above copyright
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14 # documentation and/or other materials provided with the distribution.
16 # 3. Neither the name of the copyright holder nor the names of its
17 # contributors may be used to endorse or promote products derived from
18 # this software without specific prior written permission.
20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 # TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
24 # OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 # PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
27 # PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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29 # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 # Authors: Christian Menard
36 from m5
.objects
import *
40 # Base System Architecture:
43 # +--+--+ | (see main.cc)
45 # +----------v-----------+ External Port (see sc_master_port.*)
47 # +----------+-----------+ |
54 # Create a system with a Crossbar and a simple Memory:
56 system
.membus
= IOXBar(width
= 16)
57 system
.physmem
= SimpleMemory(range = AddrRange('512MB'))
58 system
.clk_domain
= SrcClockDomain(clock
= '1.5GHz',
59 voltage_domain
= VoltageDomain(voltage
= '1V'))
61 # Create a external TLM port:
62 system
.tlm
= ExternalMaster()
63 system
.tlm
.port_type
= "tlm_master"
64 system
.tlm
.port_data
= "transactor"
66 # Route the connections:
67 system
.system_port
= system
.membus
.slave
68 system
.physmem
.port
= system
.membus
.master
69 system
.tlm
.port
= system
.membus
.slave
70 system
.mem_mode
= 'timing'
72 # Start the simulation:
73 root
= Root(full_system
= False, system
= system
)