util/tlm/examples/slave_port/tlm.py

   1 # Copyright (c) 2015, University of Kaiserslautern
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  30 #
  31 # Authors: Matthias Jung
  32
  33 import m5
  34 from m5.objects import *
  35
  36 # This configuration shows a simple setup of a TrafficGen (CPU) and an
  37 # external TLM port for SystemC co-simulation
  38 #
  39 # Base System Architecture:
  40 # +-------------+  +-----+    ^
  41 # | System Port |  | CPU |    |
  42 # +-------+-----+  +--+--+    |
  43 #         |           |       | gem5 World
  44 #         |      +----+       | (see this file)
  45 #         |      |            |
  46 # +-------v------v-------+    |
  47 # |        Membus        |    v
  48 # +----------------+-----+    External Port (see sc_slave_port.*)
  49 #                  |          ^
  50 #              +---v---+      | TLM World
  51 #              |  TLM  |      | (see sc_target.*)
  52 #              +-------+      v
  53 #
  54
  55 # Create a system with a Crossbar and a TrafficGenerator as CPU:
  56 system = System()
  57 system.membus = IOXBar(width = 16)
  58 system.physmem = SimpleMemory() # This must be instanciated, even if not needed
  59 system.cpu = TrafficGen(config_file = "tgen.cfg")
  60 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
  61     voltage_domain = VoltageDomain(voltage = '1V'))
  62
  63 # Create a external TLM port:
  64 system.tlm = ExternalSlave()
  65 system.tlm.addr_ranges = [AddrRange('512MB')]
  66 system.tlm.port_type = "tlm_slave"
  67 system.tlm.port_data = "transactor"
  68
  69 # Route the connections:
  70 system.cpu.port = system.membus.slave
  71 system.system_port = system.membus.slave
  72 system.membus.master = system.tlm.port
  73
  74 # Start the simulation:
  75 root = Root(full_system = False, system = system)
  76 root.system.mem_mode = 'timing'
  77 m5.instantiate()
  78 m5.simulate() #Simulation time specified later on commandline