util/tlm/sc_master_port.hh

   1 /*
   2  * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright notice,
  10  *    this list of conditions and the following disclaimer.
  11  *
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * 3. Neither the name of the copyright holder nor the names of its
  17  *    contributors may be used to endorse or promote products derived from
  18  *    this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
  24  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  27  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  28  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  29  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * Authors: Christian Menard
  33  */
  34
  35 #ifndef __SC_MASTER_PORT_HH__
  36 #define __SC_MASTER_PORT_HH__
  37
  38 #include <tlm_utils/peq_with_cb_and_phase.h>
  39
  40 #include <systemc>
  41 #include <tlm>
  42
  43 #include <mem/external_master.hh>
  44 #include <sc_peq.hh>
  45 #include <sim_control.hh>
  46
  47 namespace Gem5SystemC
  48 {
  49
  50 // forward declaration
  51 class Gem5MasterTransactor;
  52
  53 /**
  54  * This is a gem5 master port that translates TLM transactions to gem5 packets.
  55  *
  56  * Upon receiving a TLM transaction (b_transport, nb_transport_fw,
  57  * dbg_transport) the port generates a gem5 packet and initializes the packet
  58  * with information from the transaction payload. The original TLM payload is
  59  * added as a sender state to the gem5 packet. This way the payload can be
  60  * restored when the response packet arrives at the port.
  61  *
  62  * Special care is required, when the TLM transaction originates from a
  63  * SCSlavePort (i.e. it is a gem5 packet that enters back into the gem5 world).
  64  * This is a common scenario, when multiple gem5 CPUs communicate via a SystemC
  65  * interconnect. In this case, the master port restores the original packet
  66  * from the payload extension (added by the SCSlavePort) and forwards it to the
  67  * gem5 world. Throughout the code, this mechanism is called 'pipe through'.
  68  *
  69  * If gem5 operates in atomic mode, the master port registers the TLM blocking
  70  * interface and automatically translates non-blocking requests to blocking.
  71  * If gem5 operates in timing mode, the transactor registers the non-blocking
  72  * interface. Then, the transactor automatically translated blocking requests.
  73  * It is assumed that the mode (atomic/timing) does not change during
  74  * execution.
  75  */
  76 class SCMasterPort : public ExternalMaster::Port
  77 {
  78   private:
  79     struct TlmSenderState : public Packet::SenderState
  80     {
  81         tlm::tlm_generic_payload& trans;
  82         TlmSenderState(tlm::tlm_generic_payload& trans)
  83           : trans(trans)
  84         {
  85         }
  86     };
  87
  88     tlm_utils::peq_with_cb_and_phase<SCMasterPort> peq;
  89
  90     bool waitForRetry;
  91     tlm::tlm_generic_payload* pendingRequest;
  92     PacketPtr pendingPacket;
  93
  94     bool needToSendRetry;
  95
  96     bool responseInProgress;
  97
  98     Gem5MasterTransactor* transactor;
  99
 100     System* system;
 101
 102     Gem5SimControl& simControl;
 103
 104   protected:
 105     // payload event call back
 106     void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
 107
 108     // The TLM target interface
 109     tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
 110                                        tlm::tlm_phase& phase,
 111                                        sc_core::sc_time& t);
 112     void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& t);
 113     unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
 114     bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
 115                             tlm::tlm_dmi& dmi_data);
 116
 117     // Gem5 SCMasterPort interface
 118     bool recvTimingResp(PacketPtr pkt);
 119     void recvReqRetry();
 120     void recvRangeChange();
 121
 122   public:
 123     SCMasterPort(const std::string& name_,
 124                  const std::string& systemc_name,
 125                  ExternalMaster& owner_,
 126                  Gem5SimControl& simControl);
 127
 128     void bindToTransactor(Gem5MasterTransactor* transactor);
 129
 130     friend PayloadEvent<SCMasterPort>;
 131
 132   private:
 133     void sendEndReq(tlm::tlm_generic_payload& trans);
 134     void sendBeginResp(tlm::tlm_generic_payload& trans,
 135                        sc_core::sc_time& delay);
 136
 137     void handleBeginReq(tlm::tlm_generic_payload& trans);
 138     void handleEndResp(tlm::tlm_generic_payload& trans);
 139
 140     PacketPtr generatePacket(tlm::tlm_generic_payload& trans);
 141     void destroyPacket(PacketPtr pkt);
 142
 143     void checkTransaction(tlm::tlm_generic_payload& trans);
 144 };
 145
 146 class SCMasterPortHandler : public ExternalMaster::Handler
 147 {
 148   private:
 149     Gem5SimControl& control;
 150
 151   public:
 152     SCMasterPortHandler(Gem5SimControl& control) : control(control) {}
 153
 154     ExternalMaster::Port *getExternalPort(const std::string &name,
 155                                           ExternalMaster &owner,
 156                                           const std::string &port_data);
 157 };
 158
 159 }
 160
 161 #endif