util/tlm/slave_transactor.cc

   1 /*
   2  * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright notice,
  10  *    this list of conditions and the following disclaimer.
  11  *
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * 3. Neither the name of the copyright holder nor the names of its
  17  *    contributors may be used to endorse or promote products derived from
  18  *    this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
  24  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  27  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  28  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  29  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * Authors: Christian Menard
  33  */
  34
  35 #include "sc_slave_port.hh"
  36 #include "sim_control.hh"
  37 #include "slave_transactor.hh"
  38
  39 namespace Gem5SystemC
  40 {
  41
  42 Gem5SlaveTransactor::Gem5SlaveTransactor(sc_core::sc_module_name name,
  43                                          const std::string& portName)
  44     : sc_core::sc_module(name),
  45       socket(portName.c_str()),
  46       sim_control("sim_control"),
  47       portName(portName)
  48 {
  49     if (portName.empty()) {
  50         SC_REPORT_ERROR(name, "No port name specified!\n");
  51     }
  52 }
  53
  54 void
  55 Gem5SlaveTransactor::before_end_of_elaboration()
  56 {
  57     auto* port = sim_control->getSlavePort(portName);
  58
  59     port->bindToTransactor(this);
  60 }
  61
  62 }