util/tlm/src/sc_master_port.hh

   1 /*
   2  * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright notice,
  10  *    this list of conditions and the following disclaimer.
  11  *
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * 3. Neither the name of the copyright holder nor the names of its
  17  *    contributors may be used to endorse or promote products derived from
  18  *    this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  23  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
  24  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  26  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  27  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  28  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  29  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #ifndef __SC_MASTER_PORT_HH__
  34 #define __SC_MASTER_PORT_HH__
  35
  36 #include <tlm_utils/peq_with_cb_and_phase.h>
  37
  38 #include <systemc>
  39 #include <tlm>
  40
  41 #include "mem/external_master.hh"
  42 #include "sc_peq.hh"
  43 #include "sim_control.hh"
  44
  45 namespace Gem5SystemC
  46 {
  47
  48 // forward declaration
  49 class Gem5MasterTransactor;
  50
  51 /**
  52  * This is a gem5 master port that translates TLM transactions to gem5 packets.
  53  *
  54  * Upon receiving a TLM transaction (b_transport, nb_transport_fw,
  55  * dbg_transport) the port generates a gem5 packet and initializes the packet
  56  * with information from the transaction payload. The original TLM payload is
  57  * added as a sender state to the gem5 packet. This way the payload can be
  58  * restored when the response packet arrives at the port.
  59  *
  60  * Special care is required, when the TLM transaction originates from a
  61  * SCSlavePort (i.e. it is a gem5 packet that enters back into the gem5 world).
  62  * This is a common scenario, when multiple gem5 CPUs communicate via a SystemC
  63  * interconnect. In this case, the master port restores the original packet
  64  * from the payload extension (added by the SCSlavePort) and forwards it to the
  65  * gem5 world. Throughout the code, this mechanism is called 'pipe through'.
  66  *
  67  * If gem5 operates in atomic mode, the master port registers the TLM blocking
  68  * interface and automatically translates non-blocking requests to blocking.
  69  * If gem5 operates in timing mode, the transactor registers the non-blocking
  70  * interface. Then, the transactor automatically translated blocking requests.
  71  * It is assumed that the mode (atomic/timing) does not change during
  72  * execution.
  73  */
  74 class SCMasterPort : public ExternalMaster::Port
  75 {
  76   private:
  77     struct TlmSenderState : public Packet::SenderState
  78     {
  79         tlm::tlm_generic_payload& trans;
  80         TlmSenderState(tlm::tlm_generic_payload& trans)
  81           : trans(trans)
  82         {
  83         }
  84     };
  85
  86     tlm_utils::peq_with_cb_and_phase<SCMasterPort> peq;
  87
  88     bool waitForRetry;
  89     tlm::tlm_generic_payload* pendingRequest;
  90     PacketPtr pendingPacket;
  91
  92     bool needToSendRetry;
  93
  94     bool responseInProgress;
  95
  96     Gem5MasterTransactor* transactor;
  97
  98     System* system;
  99
 100     Gem5SimControl& simControl;
 101
 102   protected:
 103     // payload event call back
 104     void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
 105
 106     // The TLM target interface
 107     tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans,
 108                                        tlm::tlm_phase& phase,
 109                                        sc_core::sc_time& t);
 110     void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& t);
 111     unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
 112     bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans,
 113                             tlm::tlm_dmi& dmi_data);
 114
 115     // Gem5 SCMasterPort interface
 116     bool recvTimingResp(PacketPtr pkt);
 117     void recvReqRetry();
 118     void recvRangeChange();
 119
 120   public:
 121     SCMasterPort(const std::string& name_,
 122                  const std::string& systemc_name,
 123                  ExternalMaster& owner_,
 124                  Gem5SimControl& simControl);
 125
 126     void bindToTransactor(Gem5MasterTransactor* transactor);
 127
 128     friend PayloadEvent<SCMasterPort>;
 129
 130   private:
 131     void sendEndReq(tlm::tlm_generic_payload& trans);
 132     void sendBeginResp(tlm::tlm_generic_payload& trans,
 133                        sc_core::sc_time& delay);
 134
 135     void handleBeginReq(tlm::tlm_generic_payload& trans);
 136     void handleEndResp(tlm::tlm_generic_payload& trans);
 137
 138     PacketPtr generatePacket(tlm::tlm_generic_payload& trans);
 139     void destroyPacket(PacketPtr pkt);
 140
 141     void checkTransaction(tlm::tlm_generic_payload& trans);
 142 };
 143
 144 class SCMasterPortHandler : public ExternalMaster::Handler
 145 {
 146   private:
 147     Gem5SimControl& control;
 148
 149   public:
 150     SCMasterPortHandler(Gem5SimControl& control) : control(control) {}
 151
 152     ExternalMaster::Port *getExternalPort(const std::string &name,
 153                                           ExternalMaster &owner,
 154                                           const std::string &port_data);
 155 };
 156
 157 }
 158
 159 #endif