util/tlm/src/sc_slave_port.hh

   1 /*
   2  * Copyright (c) 2015, University of Kaiserslautern
   3  * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright notice,
  11  *    this list of conditions and the following disclaimer.
  12  *
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  *
  17  * 3. Neither the name of the copyright holder nor the names of its
  18  *    contributors may be used to endorse or promote products derived from
  19  *    this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  24  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
  25  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  26  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  27  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  28  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  29  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  30  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef __SC_SLAVE_PORT_HH__
  35 #define __SC_SLAVE_PORT_HH__
  36
  37 #include <systemc>
  38 #include <tlm>
  39
  40 #include "mem/external_slave.hh"
  41 #include "sc_mm.hh"
  42 #include "sc_peq.hh"
  43 #include "sim_control.hh"
  44
  45 namespace Gem5SystemC
  46 {
  47
  48 // forward declaration
  49 class Gem5SlaveTransactor;
  50
  51 /**
  52  * Test that gem5 is at the same time as SystemC
  53  */
  54 #define CAUGHT_UP do { \
  55     assert(curTick() == sc_core::sc_time_stamp().value()); \
  56 } while (0)
  57
  58 /**
  59  * This is a gem5 slave port that translates gem5 packets to TLM transactions.
  60  *
  61  * Upon receiving a packet (recvAtomic, recvTiningReq, recvFunctional) the port
  62  * creates a new TLM payload and initializes it with information from the gem5
  63  * packet. The original packet is added as an extension to the TLM payload.
  64  * Then the port issues a TLM transaction in the SystemC world. By storing the
  65  * original packet as a payload extension, the packet can be restored and send
  66  * back to the gem5 world upon receiving a response from the SystemC world.
  67  */
  68 class SCSlavePort : public ExternalSlave::Port
  69 {
  70   public:
  71     /** One instance of pe and the related callback needed */
  72     //payloadEvent<SCSlavePort> pe;
  73     void pec(PayloadEvent<SCSlavePort> * pe,
  74         tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
  75
  76     /**
  77      * A transaction after BEGIN_REQ has been sent but before END_REQ, which
  78      * is blocking the request channel (Exlusion Rule, see IEEE1666)
  79      */
  80     tlm::tlm_generic_payload *blockingRequest;
  81
  82     /**
  83      * Did another gem5 request arrive while currently blocked?
  84      * This variable is needed when a retry should happen
  85      */
  86     bool needToSendRequestRetry;
  87
  88     /**
  89      * A response which has been asked to retry by gem5 and so is blocking
  90      * the response channel
  91      */
  92     tlm::tlm_generic_payload *blockingResponse;
  93
  94   protected:
  95     /** The gem5 Port slave interface */
  96     Tick recvAtomic(PacketPtr packet);
  97     void recvFunctional(PacketPtr packet);
  98     bool recvTimingReq(PacketPtr packet);
  99     bool recvTimingSnoopResp(PacketPtr packet);
 100     void recvRespRetry();
 101     void recvFunctionalSnoop(PacketPtr packet);
 102
 103     Gem5SlaveTransactor* transactor;
 104
 105   public:
 106     /** The TLM initiator interface */
 107     tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans,
 108                                        tlm::tlm_phase& phase,
 109                                        sc_core::sc_time& t);
 110
 111     SCSlavePort(const std::string &name_,
 112                 const std::string &systemc_name,
 113                 ExternalSlave &owner_);
 114
 115     void bindToTransactor(Gem5SlaveTransactor* transactor);
 116
 117     friend PayloadEvent<SCSlavePort>;
 118 };
 119
 120 class SCSlavePortHandler : public ExternalSlave::Handler
 121 {
 122   private:
 123     Gem5SimControl& control;
 124
 125   public:
 126     SCSlavePortHandler(Gem5SimControl& control) : control(control) {}
 127
 128     ExternalSlave::Port *getExternalPort(const std::string &name,
 129                                          ExternalSlave &owner,
 130                                          const std::string &port_data);
 131 };
 132
 133 }
 134
 135 #endif // __SC_SLAVE_PORT_H__