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11 * The above copyright notice and this permission notice (including the next
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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26 * v3d driver code interacting v3dv3 simulator/fpga library.
28 * This is compiled per V3D version we support, since the register definitions
37 #include "util/macros.h"
38 #include "util/u_mm.h"
39 #include "broadcom/common/v3d_macros.h"
40 #include "v3d_simulator_wrapper.h"
41 #include "drm-shim/drm_shim.h"
42 #include "drm-uapi/v3d_drm.h"
45 #define HW_REGISTER_RO(x) (x)
46 #define HW_REGISTER_RW(x) (x)
48 #include "libs/core/v3d/registers/4.1.34.0/v3d.h"
50 #include "libs/core/v3d/registers/3.3.0.0/v3d.h"
53 #define V3D_WRITE(reg, val) v3d_hw_write_reg(v3d.hw, reg, val)
54 #define V3D_READ(reg) v3d_hw_read_reg(v3d.hw, reg)
59 if (!v3d_hw_has_gca(v3d
.hw
))
63 uint32_t gca_ctrl
= V3D_READ(V3D_GCA_CACHE_CTRL
);
65 V3D_WRITE(V3D_GCA_CACHE_CTRL
, gca_ctrl
| V3D_GCA_CACHE_CTRL_FLUSH_SET
);
66 V3D_WRITE(V3D_GCA_CACHE_CTRL
, gca_ctrl
& ~V3D_GCA_CACHE_CTRL_FLUSH_SET
);
70 /* Invalidates the L2 cache. This is a read-only cache. */
74 V3D_WRITE(V3D_CTL_0_L2CACTL
,
75 V3D_CTL_0_L2CACTL_L2CCLR_SET
|
76 V3D_CTL_0_L2CACTL_L2CENA_SET
);
79 /* Invalidates texture L2 cachelines */
83 V3D_WRITE(V3D_CTL_0_L2TFLSTA
, 0);
84 V3D_WRITE(V3D_CTL_0_L2TFLEND
, ~0);
85 V3D_WRITE(V3D_CTL_0_L2TCACTL
,
86 V3D_CTL_0_L2TCACTL_L2TFLS_SET
|
87 (0 << V3D_CTL_0_L2TCACTL_L2TFLM_LSB
));
90 /* Invalidates the slice caches. These are read-only caches. */
92 v3d_flush_slices(void)
94 V3D_WRITE(V3D_CTL_0_SLCACTL
, ~0);
98 v3d_flush_caches(void)
107 v3d_simulator_copy_in_handle(struct shim_fd
*shim_fd
, int handle
)
112 struct v3d_bo
*bo
= v3d_bo_lookup(shim_fd
, handle
);
114 memcpy(bo
->sim_vaddr
, bo
->gem_vaddr
, bo
->base
.size
);
118 v3d_simulator_copy_out_handle(struct shim_fd
*shim_fd
, int handle
)
123 struct v3d_bo
*bo
= v3d_bo_lookup(shim_fd
, handle
);
125 memcpy(bo
->gem_vaddr
, bo
->sim_vaddr
, bo
->base
.size
);
129 v3dX(v3d_ioctl_submit_cl
)(int fd
, unsigned long request
, void *arg
)
131 struct shim_fd
*shim_fd
= drm_shim_fd_lookup(fd
);
132 struct drm_v3d_submit_cl
*submit
= arg
;
133 uint32_t *bo_handles
= (uint32_t *)(uintptr_t)submit
->bo_handles
;
135 for (int i
= 0; i
< submit
->bo_handle_count
; i
++)
136 v3d_simulator_copy_in_handle(shim_fd
, bo_handles
[i
]);
141 V3D_WRITE(V3D_CLE_0_CT0QMA
, submit
->qma
);
142 V3D_WRITE(V3D_CLE_0_CT0QMS
, submit
->qms
);
144 #if V3D_VERSION >= 41
146 V3D_WRITE(V3D_CLE_0_CT0QTS
,
147 V3D_CLE_0_CT0QTS_CTQTSEN_SET
|
152 fprintf(stderr
, "submit %x..%x!\n", submit
->bcl_start
, submit
->bcl_end
);
154 V3D_WRITE(V3D_CLE_0_CT0QBA
, submit
->bcl_start
);
155 V3D_WRITE(V3D_CLE_0_CT0QEA
, submit
->bcl_end
);
157 /* Wait for bin to complete before firing render, as it seems the
158 * simulator doesn't implement the semaphores.
160 while (V3D_READ(V3D_CLE_0_CT0CA
) !=
161 V3D_READ(V3D_CLE_0_CT0EA
)) {
165 fprintf(stderr
, "submit %x..%x!\n", submit
->rcl_start
, submit
->rcl_end
);
169 V3D_WRITE(V3D_CLE_0_CT1QBA
, submit
->rcl_start
);
170 V3D_WRITE(V3D_CLE_0_CT1QEA
, submit
->rcl_end
);
172 while (V3D_READ(V3D_CLE_0_CT1CA
) !=
173 V3D_READ(V3D_CLE_0_CT1EA
)) {
177 for (int i
= 0; i
< submit
->bo_handle_count
; i
++)
178 v3d_simulator_copy_out_handle(shim_fd
, bo_handles
[i
]);
184 v3dX(v3d_ioctl_submit_tfu
)(int fd
, unsigned long request
, void *arg
)
186 struct shim_fd
*shim_fd
= drm_shim_fd_lookup(fd
);
187 struct drm_v3d_submit_tfu
*submit
= arg
;
189 v3d_simulator_copy_in_handle(shim_fd
, submit
->bo_handles
[0]);
190 v3d_simulator_copy_in_handle(shim_fd
, submit
->bo_handles
[1]);
191 v3d_simulator_copy_in_handle(shim_fd
, submit
->bo_handles
[2]);
192 v3d_simulator_copy_in_handle(shim_fd
, submit
->bo_handles
[3]);
194 int last_vtct
= V3D_READ(V3D_TFU_CS
) & V3D_TFU_CS_CVTCT_SET
;
196 V3D_WRITE(V3D_TFU_IIA
, submit
->iia
);
197 V3D_WRITE(V3D_TFU_IIS
, submit
->iis
);
198 V3D_WRITE(V3D_TFU_ICA
, submit
->ica
);
199 V3D_WRITE(V3D_TFU_IUA
, submit
->iua
);
200 V3D_WRITE(V3D_TFU_IOA
, submit
->ioa
);
201 V3D_WRITE(V3D_TFU_IOS
, submit
->ios
);
202 V3D_WRITE(V3D_TFU_COEF0
, submit
->coef
[0]);
203 V3D_WRITE(V3D_TFU_COEF1
, submit
->coef
[1]);
204 V3D_WRITE(V3D_TFU_COEF2
, submit
->coef
[2]);
205 V3D_WRITE(V3D_TFU_COEF3
, submit
->coef
[3]);
207 V3D_WRITE(V3D_TFU_ICFG
, submit
->icfg
);
209 while ((V3D_READ(V3D_TFU_CS
) & V3D_TFU_CS_CVTCT_SET
) == last_vtct
) {
213 v3d_simulator_copy_out_handle(shim_fd
, submit
->bo_handles
[0]);
219 v3dX(v3d_ioctl_create_bo
)(int fd
, unsigned long request
, void *arg
)
221 struct shim_fd
*shim_fd
= drm_shim_fd_lookup(fd
);
222 struct drm_v3d_create_bo
*create
= arg
;
223 struct v3d_bo
*bo
= calloc(1, sizeof(*bo
));
225 drm_shim_bo_init(&bo
->base
, create
->size
);
226 bo
->offset
= util_vma_heap_alloc(&v3d
.heap
, create
->size
, 4096);
230 bo
->sim_vaddr
= v3d
.mem
+ bo
->offset
- v3d
.mem_base
;
232 /* Place a mapping of the BO inside of the simulator's address space
233 * for V3D memory. This lets us avoid copy in/out for simpenrose, but
234 * I'm betting we'll need something else for FPGA.
236 void *sim_addr
= v3d
.mem
+ bo
->block
->ofs
;
237 void *mmap_ret
= mmap(sim_addr
, create
->size
, PROT_READ
| PROT_WRITE
,
238 MAP_SHARED
| MAP_FIXED
, bo
->base
.fd
, 0);
239 assert(mmap_ret
== sim_addr
);
241 /* Make a simulator-private mapping of the shim GEM object. */
242 bo
->gem_vaddr
= mmap(NULL
, bo
->base
.size
,
243 PROT_READ
| PROT_WRITE
,
246 if (bo
->gem_vaddr
== MAP_FAILED
) {
247 fprintf(stderr
, "v3d: mmap of shim bo failed\n");
252 create
->offset
= bo
->offset
;
253 create
->handle
= drm_shim_bo_get_handle(shim_fd
, &bo
->base
);
255 drm_shim_bo_put(&bo
->base
);
261 v3dX(v3d_ioctl_get_param
)(int fd
, unsigned long request
, void *arg
)
263 struct drm_v3d_get_param
*gp
= arg
;
264 static const uint32_t reg_map
[] = {
265 [DRM_V3D_PARAM_V3D_UIFCFG
] = V3D_HUB_CTL_UIFCFG
,
266 [DRM_V3D_PARAM_V3D_HUB_IDENT1
] = V3D_HUB_CTL_IDENT1
,
267 [DRM_V3D_PARAM_V3D_HUB_IDENT2
] = V3D_HUB_CTL_IDENT2
,
268 [DRM_V3D_PARAM_V3D_HUB_IDENT3
] = V3D_HUB_CTL_IDENT3
,
269 [DRM_V3D_PARAM_V3D_CORE0_IDENT0
] = V3D_CTL_0_IDENT0
,
270 [DRM_V3D_PARAM_V3D_CORE0_IDENT1
] = V3D_CTL_0_IDENT1
,
271 [DRM_V3D_PARAM_V3D_CORE0_IDENT2
] = V3D_CTL_0_IDENT2
,
275 case DRM_V3D_PARAM_SUPPORTS_TFU
:
280 if (gp
->param
< ARRAY_SIZE(reg_map
) && reg_map
[gp
->param
]) {
281 gp
->value
= V3D_READ(reg_map
[gp
->param
]);
285 fprintf(stderr
, "Unknown DRM_IOCTL_V3D_GET_PARAM %d\n", gp
->param
);
289 static ioctl_fn_t driver_ioctls
[] = {
290 [DRM_V3D_SUBMIT_CL
] = v3dX(v3d_ioctl_submit_cl
),
291 [DRM_V3D_SUBMIT_TFU
] = v3dX(v3d_ioctl_submit_tfu
),
292 [DRM_V3D_WAIT_BO
] = v3d_ioctl_wait_bo
,
293 [DRM_V3D_CREATE_BO
] = v3dX(v3d_ioctl_create_bo
),
294 [DRM_V3D_GET_PARAM
] = v3dX(v3d_ioctl_get_param
),
295 [DRM_V3D_MMAP_BO
] = v3d_ioctl_mmap_bo
,
296 [DRM_V3D_GET_BO_OFFSET
] = v3d_ioctl_get_bo_offset
,
300 v3d_isr(uint32_t hub_status
)
302 /* Check the per-core bits */
303 if (hub_status
& (1 << 0)) {
304 uint32_t core_status
= V3D_READ(V3D_CTL_0_INT_STS
);
306 if (core_status
& V3D_CTL_0_INT_STS_INT_GMPV_SET
) {
307 fprintf(stderr
, "GMP violation at 0x%08x\n",
308 V3D_READ(V3D_GMP_0_VIO_ADDR
));
312 "Unexpected ISR with core status 0x%08x\n",
322 v3dX(simulator_init_regs
)(void)
324 #if V3D_VERSION == 33
325 /* Set OVRTMUOUT to match kernel behavior.
327 * This means that the texture sampler uniform configuration's tmu
328 * output type field is used, instead of using the hardware default
329 * behavior based on the texture type. If you want the default
330 * behavior, you can still put "2" in the indirect texture state's
333 V3D_WRITE(V3D_CTL_0_MISCCFG
, V3D_CTL_1_MISCCFG_OVRTMUOUT_SET
);
336 uint32_t core_interrupts
= V3D_CTL_0_INT_STS_INT_GMPV_SET
;
337 V3D_WRITE(V3D_CTL_0_INT_MSK_SET
, ~core_interrupts
);
338 V3D_WRITE(V3D_CTL_0_INT_MSK_CLR
, core_interrupts
);
340 v3d_hw_set_isr(v3d
.hw
, v3d_isr
);
344 v3d_bo_free(struct shim_bo
*shim_bo
)
346 struct v3d_bo
*bo
= v3d_bo(shim_bo
);
349 munmap(bo
->gem_vaddr
, shim_bo
->size
);
351 util_vma_heap_free(&v3d
.heap
, bo
->offset
, bo
->base
.size
);
355 v3dX(drm_shim_driver_init
)(void)
357 shim_device
.driver_ioctls
= driver_ioctls
;
358 shim_device
.driver_ioctl_count
= ARRAY_SIZE(driver_ioctls
);
360 shim_device
.driver_bo_free
= v3d_bo_free
;
362 /* Allocate a gig of memory to play in. */
363 v3d_hw_alloc_mem(v3d
.hw
, 1024 * 1024 * 1024);
365 v3d_hw_get_mem(v3d
.hw
, &v3d
.mem_size
,
367 util_vma_heap_init(&v3d
.heap
, 4096, v3d
.mem_size
- 4096);
369 v3dX(simulator_init_regs
)();