Add Tercel PHY reset synchronization
[microwatt.git] / verilator / microwatt-verilator.cpp
1 #include <stdlib.h>
2 #include "Vmicrowatt.h"
3 #include "verilated.h"
4 #include "verilated_vcd_c.h"
5
6 /*
7 * Current simulation time
8 * This is a 64-bit integer to reduce wrap over issues and
9 * allow modulus. You can also use a double, if you wish.
10 */
11 vluint64_t main_time = 0;
12
13 /*
14 * Called by $time in Verilog
15 * converts to double, to match
16 * what SystemC does
17 */
18 double sc_time_stamp(void)
19 {
20 return main_time;
21 }
22
23 #if VM_TRACE
24 VerilatedVcdC *tfp;
25 #endif
26
27 void tick(Vmicrowatt *top)
28 {
29 top->ext_clk = 1;
30 top->eval();
31 #if VM_TRACE
32 if (tfp)
33 tfp->dump((double) main_time);
34 #endif
35 main_time++;
36
37 top->ext_clk = 0;
38 top->eval();
39 #if VM_TRACE
40 if (tfp)
41 tfp->dump((double) main_time);
42 #endif
43 main_time++;
44 }
45
46 void uart_tx(unsigned char tx);
47 unsigned char uart_rx(void);
48
49 int main(int argc, char **argv)
50 {
51 Verilated::commandArgs(argc, argv);
52
53 // init top verilog instance
54 Vmicrowatt* top = new Vmicrowatt;
55
56 #if VM_TRACE
57 // init trace dump
58 Verilated::traceEverOn(true);
59 tfp = new VerilatedVcdC;
60 top->trace(tfp, 99);
61 tfp->open("microwatt-verilator.vcd");
62 #endif
63
64 // Reset
65 top->ext_rst = 0;
66 for (unsigned long i = 0; i < 5; i++)
67 tick(top);
68 top->ext_rst = 1;
69
70 while(!Verilated::gotFinish()) {
71 tick(top);
72
73 uart_tx(top->uart0_txd);
74 top->uart0_rxd = uart_rx();
75 }
76
77 #if VM_TRACE
78 tfp->close();
79 delete tfp;
80 #endif
81
82 delete top;
83 }