2 use ieee.std_logic_1164.all;
5 use work.wishbone_types.all;
7 -- TODO: Use an array of master/slaves with parametric size
8 entity wishbone_arbiter is
9 port (clk : in std_ulogic;
12 wb1_in : in wishbone_master_out;
13 wb1_out : out wishbone_slave_out;
15 wb2_in : in wishbone_master_out;
16 wb2_out : out wishbone_slave_out;
18 wb3_in : in wishbone_master_out;
19 wb3_out : out wishbone_slave_out;
21 wb_out : out wishbone_master_out;
22 wb_in : in wishbone_slave_out
26 architecture behave of wishbone_arbiter is
27 type wishbone_arbiter_state_t is (IDLE, WB1_BUSY, WB2_BUSY, WB3_BUSY);
28 signal state : wishbone_arbiter_state_t := IDLE;
31 wishbone_muxes: process(state, wb_in, wb1_in, wb2_in, wb3_in)
33 -- Requests from masters are fully muxed
34 wb_out <= wb1_in when state = WB1_BUSY else
35 wb2_in when state = WB2_BUSY else
36 wb3_in when state = WB3_BUSY else
37 wishbone_master_out_init;
39 -- Responses from slave don't need to mux the data bus
40 wb1_out.dat <= wb_in.dat;
41 wb2_out.dat <= wb_in.dat;
42 wb3_out.dat <= wb_in.dat;
43 wb1_out.ack <= wb_in.ack when state = WB1_BUSY else '0';
44 wb2_out.ack <= wb_in.ack when state = WB2_BUSY else '0';
45 wb3_out.ack <= wb_in.ack when state = WB3_BUSY else '0';
48 wishbone_arbiter_process: process(clk)
50 if rising_edge(clk) then
56 if wb1_in.cyc = '1' then
58 elsif wb2_in.cyc = '1' then
60 elsif wb3_in.cyc = '1' then
64 if wb1_in.cyc = '0' then
68 if wb2_in.cyc = '0' then
72 if wb3_in.cyc = '0' then