2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.wishbone_types.all;
8 entity wishbone_bram_tb is
11 architecture behave of wishbone_bram_tb is
12 signal clk : std_ulogic;
13 signal rst : std_ulogic := '1';
15 constant clk_period : time := 10 ns;
17 signal w_in : wishbone_slave_out;
18 signal w_out : wishbone_master_out;
20 impure function to_adr(a: integer) return std_ulogic_vector is
22 return std_ulogic_vector(to_unsigned(a, w_out.adr'length));
25 simple_ram_0: entity work.wishbone_bram_wrapper
27 RAM_INIT_FILE => "wishbone_bram_tb.bin",
40 wait for clk_period / 2;
42 wait for clk_period / 2;
47 w_out.adr <= (others => '0');
48 w_out.dat <= (others => '0');
51 w_out.sel <= (others => '0');
54 wait until rising_edge(clk);
56 wait until rising_edge(clk);
62 w_out.sel <= "11111111";
63 w_out.adr <= to_adr(0);
64 assert w_in.ack = '0';
65 wait until rising_edge(clk);
67 wait until rising_edge(clk);
68 wait until rising_edge(clk);
69 assert w_in.ack = '1';
70 assert w_in.dat(63 downto 0) = x"0706050403020100" report to_hstring(w_in.dat);
71 wait until rising_edge(clk);
72 assert w_in.ack = '0';
76 w_out.sel <= "11111111";
77 w_out.adr <= to_adr(8);
78 assert w_in.ack = '0';
79 wait until rising_edge(clk);
81 wait until rising_edge(clk);
82 wait until rising_edge(clk);
83 assert w_in.ack = '1';
84 assert w_in.dat(63 downto 0) = x"0F0E0D0C0B0A0908" report to_hstring(w_in.dat);
85 wait until rising_edge(clk);
86 assert w_in.ack = '0';
88 -- Test write byte at 0
90 w_out.sel <= "00000001";
91 w_out.adr <= to_adr(0);
93 w_out.dat(7 downto 0) <= x"0F";
94 assert w_in.ack = '0';
95 wait until rising_edge(clk);
97 wait until rising_edge(clk) and w_in.ack = '1';
98 wait until rising_edge(clk);
99 assert w_in.ack = '0';
103 w_out.sel <= "11111111";
104 w_out.adr <= to_adr(0);
106 assert w_in.ack = '0';
107 wait until rising_edge(clk);
109 wait until rising_edge(clk);
110 wait until rising_edge(clk);
111 assert w_in.ack = '1';
112 assert w_in.dat(63 downto 0) = x"070605040302010F" report to_hstring(w_in.dat);
113 wait until rising_edge(clk);
114 assert w_in.ack = '0';
116 -- Test write dword at 4
118 w_out.sel <= "11110000";
119 w_out.adr <= to_adr(0);
121 w_out.dat(63 downto 32) <= x"BAADFEED";
122 assert w_in.ack = '0';
123 wait until rising_edge(clk);
125 wait until rising_edge(clk) and w_in.ack = '1';
126 wait until rising_edge(clk);
127 assert w_in.ack = '0';
131 w_out.sel <= "11111111";
132 w_out.adr <= to_adr(0);
134 assert w_in.ack = '0';
135 wait until rising_edge(clk);
137 wait until rising_edge(clk);
138 wait until rising_edge(clk);
139 assert w_in.ack = '1';
140 assert w_in.dat(63 downto 0) = x"BAADFEED0302010F" report to_hstring(w_in.dat);
141 wait until rising_edge(clk);
142 assert w_in.ack = '0';
144 -- Test write qword at 8
146 w_out.sel <= "11111111";
147 w_out.adr <= to_adr(8);
149 w_out.dat(63 downto 0) <= x"0001020304050607";
150 assert w_in.ack = '0';
151 wait until rising_edge(clk);
153 wait until rising_edge(clk) and w_in.ack = '1';
154 wait until rising_edge(clk);
155 assert w_in.ack = '0';
159 w_out.sel <= "11111111";
160 w_out.adr <= to_adr(8);
162 assert w_in.ack = '0';
163 wait until rising_edge(clk);
165 wait until rising_edge(clk);
166 wait until rising_edge(clk);
167 assert w_in.ack = '1';
168 assert w_in.dat(63 downto 0) = x"0001020304050607" report to_hstring(w_in.dat);
169 wait until rising_edge(clk);
170 assert w_in.ack = '0';