2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
8 use work.wishbone_types.all;
10 --! @brief Simple memory module for use in Wishbone-based systems.
11 entity wishbone_bram_wrapper is
13 MEMORY_SIZE : natural := 4096; --! Memory size in bytes.
14 RAM_INIT_FILE : string
20 -- Wishbone interface:
21 wishbone_in : in wishbone_master_out;
22 wishbone_out : out wishbone_slave_out
24 end entity wishbone_bram_wrapper;
26 architecture behaviour of wishbone_bram_wrapper is
27 constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
30 signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);
31 signal ram_we : std_ulogic;
32 signal ram_re : std_ulogic;
35 signal ack, ack_buf : std_ulogic;
38 -- Actual RAM template
39 ram_0: entity work.main_bram
42 HEIGHT_BITS => ram_addr_bits,
43 MEMORY_SIZE => MEMORY_SIZE,
44 RAM_INIT_FILE => RAM_INIT_FILE
49 di => wishbone_in.dat,
50 do => wishbone_out.dat,
51 sel => wishbone_in.sel,
57 ram_addr <= wishbone_in.adr(ram_addr_bits + 2 downto 3);
58 ram_we <= wishbone_in.stb and wishbone_in.cyc and wishbone_in.we;
59 ram_re <= wishbone_in.stb and wishbone_in.cyc and not wishbone_in.we;
60 wishbone_out.stall <= '0';
61 wishbone_out.ack <= ack_buf;
65 if rising_edge(clk) then
66 if rst = '1' or wishbone_in.cyc = '0' then
70 -- On loads, we have a delay cycle due to BRAM bufferring
71 -- but not on stores. So try to send an early ack on a
72 -- store if we aren't behind an existing load ack.
74 if ram_we = '1' and ack = '0' then
77 ack <= wishbone_in.stb;
84 end architecture behaviour;