2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.wishbone_types.all;
8 entity wishbone_debug_master is
9 port(clk : in std_ulogic;
12 -- Debug bus interface
13 dmi_addr : in std_ulogic_vector(1 downto 0);
14 dmi_din : in std_ulogic_vector(63 downto 0);
15 dmi_dout : out std_ulogic_vector(63 downto 0);
16 dmi_req : in std_ulogic;
17 dmi_wr : in std_ulogic;
18 dmi_ack : out std_ulogic;
20 -- Wishbone master interface
21 wb_out : out wishbone_master_out;
22 wb_in : in wishbone_slave_out
24 end entity wishbone_debug_master;
26 architecture behaviour of wishbone_debug_master is
28 -- ** Register offsets definitions. All registers are 64-bit
29 constant DBG_WB_ADDR : std_ulogic_vector(1 downto 0) := "00";
30 constant DBG_WB_DATA : std_ulogic_vector(1 downto 0) := "01";
31 constant DBG_WB_CTRL : std_ulogic_vector(1 downto 0) := "10";
32 constant DBG_WB_RSVD : std_ulogic_vector(1 downto 0) := "11";
36 -- bit 0..7 : SEL bits (byte enables)
37 -- bit 8 : address auto-increment
38 -- bit 10..9 : auto-increment value:
44 -- ** Address and control registers and read data
45 signal reg_addr : std_ulogic_vector(63 downto 0);
46 signal reg_ctrl_out : std_ulogic_vector(63 downto 0);
47 signal reg_ctrl : std_ulogic_vector(10 downto 0);
48 signal data_latch : std_ulogic_vector(63 downto 0);
50 type state_t is (IDLE, WB_CYCLE, DMI_WAIT);
51 signal state : state_t;
55 -- Hard wire unused bits to 0
56 reg_ctrl_out <= (63 downto 11 => '0',
57 10 downto 0 => reg_ctrl);
60 with dmi_addr select dmi_dout <=
61 reg_addr when DBG_WB_ADDR,
62 data_latch when DBG_WB_DATA,
63 reg_ctrl_out when DBG_WB_CTRL,
64 (others => '0') when others;
66 -- ADDR and CTRL register writes
67 reg_write : process(clk)
68 subtype autoinc_inc_t is integer range 1 to 8;
69 function decode_autoinc(c : std_ulogic_vector(1 downto 0))
70 return autoinc_inc_t is
73 when "00" => return 1;
74 when "01" => return 2;
75 when "10" => return 4;
76 when "11" => return 8;
77 -- Below shouldn't be necessary but GHDL complains
78 when others => return 8;
80 end function decode_autoinc;
82 if rising_edge(clk) then
84 reg_addr <= (others => '0');
85 reg_ctrl <= (others => '0');
86 else -- Standard register writes
87 if dmi_req and dmi_wr then
88 if dmi_addr = DBG_WB_ADDR then
90 elsif dmi_addr = DBG_WB_CTRL then
91 reg_ctrl <= dmi_din(10 downto 0);
93 elsif state = WB_CYCLE and (wb_in.ack and reg_ctrl(8))= '1' then
94 -- Address register auto-increment
95 reg_addr <= std_ulogic_vector(unsigned(reg_addr) +
96 decode_autoinc(reg_ctrl(10 downto 9)));
102 -- ACK is hard wired to req for register writes. For data read/writes
103 -- (aka commands), it's sent when the state machine got the WB ack.
105 -- Note: We never set it to 1, we just pass dmi_req back when acking.
106 -- This fullfills two purposes:
108 -- * Avoids polluting the ack signal when another DMI slave is
109 -- selected. This allows the decoder to just OR all the acks
110 -- together rather than mux them.
112 -- * Makes ack go down on the same cycle as req goes down, thus
113 -- saving a clock cycle. This is safe because we know that
114 -- the state machine will no longer be in DMI_WAIT state on
115 -- the next cycle, so we won't be bouncing the signal back up.
117 dmi_ack <= dmi_req when (dmi_addr /= DBG_WB_DATA or state = DMI_WAIT) else '0';
119 -- Some WB signals are direct wires from registers or DMI
120 wb_out.adr <= reg_addr;
121 wb_out.dat <= dmi_din;
122 wb_out.sel <= reg_ctrl(7 downto 0);
125 -- We always move WB cyc and stb simultaneously (no pipelining yet...)
126 wb_out.cyc <= '1' when state = WB_CYCLE else '0';
127 wb_out.stb <= '1' when state = WB_CYCLE else '0';
129 -- Data latch. WB will take the read data away as soon as the cycle
130 -- terminates but we must maintain it on DMI until req goes down, so
131 -- we latch it. (Q: Should we move that latch to dmi_dtm itself ?)
133 latch_reads : process(clk)
135 if rising_edge(clk) then
136 if state = WB_CYCLE and wb_in.ack = '1' and dmi_wr = '0' then
137 data_latch <= wb_in.dat;
142 -- Command state machine (generate wb_cyc)
143 wb_trigger : process(clk)
145 if rising_edge(clk) then
151 if dmi_req = '1' and dmi_addr = DBG_WB_DATA then
159 if dmi_req = '0' then
166 end architecture behaviour;