wishbone_debug_master.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.wishbone_types.all;
   7
   8 entity wishbone_debug_master is
   9     port(clk    : in std_ulogic;
  10          rst    : in std_ulogic;
  11
  12          -- Debug bus interface
  13          dmi_addr       : in std_ulogic_vector(1 downto 0);
  14          dmi_din        : in std_ulogic_vector(63 downto 0);
  15          dmi_dout       : out std_ulogic_vector(63 downto 0);
  16          dmi_req        : in std_ulogic;
  17          dmi_wr         : in std_ulogic;
  18          dmi_ack        : out std_ulogic;
  19
  20          -- Wishbone master interface
  21          wb_out  : out wishbone_master_out;
  22          wb_in   : in wishbone_slave_out
  23          );
  24 end entity wishbone_debug_master;
  25
  26 architecture behaviour of wishbone_debug_master is
  27
  28     -- ** Register offsets definitions. All registers are 64-bit
  29     constant DBG_WB_ADDR        : std_ulogic_vector(1 downto 0) := "00";
  30     constant DBG_WB_DATA        : std_ulogic_vector(1 downto 0) := "01";
  31     constant DBG_WB_CTRL        : std_ulogic_vector(1 downto 0) := "10";
  32     constant DBG_WB_RSVD        : std_ulogic_vector(1 downto 0) := "11";
  33
  34     -- CTRL register:
  35     --
  36     -- bit  0..7 : SEL bits (byte enables)
  37     -- bit     8 : address auto-increment
  38     -- bit 10..9 : auto-increment value:
  39     --                00 - +1
  40     --                01 - +2
  41     --                10 - +4
  42     --                11 - +8
  43
  44     -- ** Address and control registers and read data
  45     signal reg_addr             : std_ulogic_vector(63 downto 0);
  46     signal reg_ctrl_out         : std_ulogic_vector(63 downto 0);
  47     signal reg_ctrl             : std_ulogic_vector(10 downto 0);
  48     signal data_latch           : std_ulogic_vector(63 downto 0);
  49
  50     type state_t is (IDLE, WB_CYCLE, DMI_WAIT);
  51     signal state : state_t;
  52
  53 begin
  54
  55     -- Hard wire unused bits to 0
  56     reg_ctrl_out <= (63 downto 11 => '0',
  57                      10 downto  0 => reg_ctrl);
  58
  59     -- DMI read data mux
  60     with dmi_addr select dmi_dout <=
  61         reg_addr        when DBG_WB_ADDR,
  62         data_latch      when DBG_WB_DATA,
  63         reg_ctrl_out    when DBG_WB_CTRL,
  64         (others => '0') when others;
  65
  66     -- ADDR and CTRL register writes
  67     reg_write : process(clk)
  68         subtype autoinc_inc_t is integer range 1 to 8;
  69         function decode_autoinc(c : std_ulogic_vector(1 downto 0))
  70             return autoinc_inc_t is
  71         begin
  72             case c is
  73             when "00" => return 1;
  74             when "01" => return 2;
  75             when "10" => return 4;
  76             when "11" => return 8;
  77             -- Below shouldn't be necessary but GHDL complains
  78             when others => return 8;
  79             end case;
  80         end function decode_autoinc;
  81     begin
  82         if rising_edge(clk) then
  83             if (rst) then
  84                 reg_addr <= (others => '0');
  85                 reg_ctrl <= (others => '0');
  86             else            -- Standard register writes
  87                 if dmi_req and dmi_wr then
  88                     if dmi_addr = DBG_WB_ADDR then
  89                         reg_addr <= dmi_din;
  90                     elsif dmi_addr = DBG_WB_CTRL then
  91                         reg_ctrl <= dmi_din(10 downto 0);
  92                     end if;
  93                 end if;
  94                 -- Address register auto-increment
  95                 if state = WB_CYCLE and (wb_in.ack and reg_ctrl(8))= '1'  then
  96                     reg_addr <= std_ulogic_vector(unsigned(reg_addr) +
  97                                                   decode_autoinc(reg_ctrl(10 downto 9)));
  98                 end if;
  99             end if;
 100         end if;
 101     end process;
 102
 103     -- ACK is hard wired to req for register writes. For data read/writes
 104     -- (aka commands), it's sent when the state machine got the WB ack.
 105     --
 106     -- Note: We never set it to 1, we just pass dmi_req back when acking.
 107     --       This fullfills two purposes:
 108     --
 109     --        * Avoids polluting the ack signal when another DMI slave is
 110     --          selected. This allows the decoder to just OR all the acks
 111     --          together rather than mux them.
 112     --
 113     --        * Makes ack go down on the same cycle as req goes down, thus
 114     --          saving a clock cycle. This is safe because we know that
 115     --          the state machine will no longer be in DMI_WAIT state on
 116     --          the next cycle, so we won't be bouncing the signal back up.
 117     --
 118     dmi_ack <= dmi_req when (dmi_addr /= DBG_WB_DATA or state = DMI_WAIT) else '0';
 119
 120         -- Some WB signals are direct wires from registers or DMI
 121     wb_out.adr <= reg_addr;
 122     wb_out.dat <= dmi_din;
 123     wb_out.sel <= reg_ctrl(7 downto 0);
 124     wb_out.we  <= dmi_wr;
 125
 126     -- We always move WB cyc and stb simultaneously (no pipelining yet...)
 127     wb_out.cyc <= '1' when state = WB_CYCLE else '0';
 128     wb_out.stb <= '1' when state = WB_CYCLE else '0';
 129
 130     -- Data latch. WB will take the read data away as soon as the cycle
 131     -- terminates but we must maintain it on DMI until req goes down, so
 132     -- we latch it. (Q: Should we move that latch to dmi_dtm itself ?)
 133     --
 134     latch_reads : process(clk)
 135     begin
 136         if rising_edge(clk) then
 137             if state = WB_CYCLE and wb_in.ack = '1' and dmi_wr = '0' then
 138                 data_latch <= wb_in.dat;
 139             end if;
 140         end if;
 141     end process;
 142
 143     -- Command state machine (generate wb_cyc)
 144     wb_trigger : process(clk)
 145     begin
 146         if rising_edge(clk) then
 147             if (rst) then
 148                 state <= IDLE;
 149             else
 150                 case state is
 151                 when IDLE =>
 152                     if dmi_req = '1' and dmi_addr = DBG_WB_DATA then
 153                         state <= WB_CYCLE;
 154                     end if;
 155                 when WB_CYCLE =>
 156                     if wb_in.ack then
 157                         state <= DMI_WAIT;
 158                     end if;
 159                 when DMI_WAIT =>
 160                     if dmi_req = '0' then
 161                         state <= IDLE;
 162                     end if;
 163                 end case;
 164             end if;
 165         end if;
 166     end process;
 167 end architecture behaviour;