writeback.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.common.all;
   6
   7 entity writeback is
   8         port (
   9                 clk          : in std_ulogic;
  10
  11                 e_in         : in Execute2ToWritebackType;
  12                 l_in         : in Loadstore2ToWritebackType;
  13                 m_in         : in MultiplyToWritebackType;
  14
  15                 w_out        : out WritebackToRegisterFileType;
  16                 c_out        : out WritebackToCrFileType;
  17
  18                 complete_out : out std_ulogic
  19         );
  20 end entity writeback;
  21
  22 architecture behaviour of writeback is
  23         signal e     : Execute2ToWritebackType;
  24         signal l     : Loadstore2ToWritebackType;
  25         signal m     : MultiplyToWritebackType;
  26         signal w_tmp : WritebackToRegisterFileType;
  27         signal c_tmp : WritebackToCrFileType;
  28 begin
  29         writeback_0: process(clk)
  30         begin
  31                 if rising_edge(clk) then
  32                         e <= e_in;
  33                         l <= l_in;
  34                         m <= m_in;
  35                 end if;
  36         end process;
  37
  38         w_out <= w_tmp;
  39         c_out <= c_tmp;
  40
  41         complete_out <= '1' when e.valid or l.valid or m.valid else '0';
  42
  43         writeback_1: process(all)
  44         begin
  45                 --assert (unsigned(w.valid) + unsigned(l.valid) + unsigned(m.valid)) <= 1;
  46                 --assert not(w.write_enable = '1' and l.write_enable = '1');
  47
  48                 w_tmp <= WritebackToRegisterFileInit;
  49                 c_tmp <= WritebackToCrFileInit;
  50
  51                 if e.valid = '1' then
  52                         if e.write_enable = '1' then
  53                                 w_tmp.write_reg <= e.write_reg;
  54                                 w_tmp.write_data <= e.write_data;
  55                                 w_tmp.write_enable <= '1';
  56                         end if;
  57
  58                         if e.write_cr_enable = '1' then
  59                                 c_tmp.write_cr_enable <= '1';
  60                                 c_tmp.write_cr_mask <= e.write_cr_mask;
  61                                 c_tmp.write_cr_data <= e.write_cr_data;
  62                         end if;
  63                 end if;
  64
  65                 if l.valid = '1' and l.write_enable = '1' then
  66                         w_tmp.write_reg <= l.write_reg;
  67                         w_tmp.write_data <= l.write_data;
  68                         w_tmp.write_enable <= '1';
  69                 end if;
  70                 if l.valid = '1' and l.write_enable2 = '1' then
  71                         w_tmp.write_reg2 <= l.write_reg2;
  72                         w_tmp.write_data2 <= l.write_data2;
  73                         w_tmp.write_enable2 <= '1';
  74                 end if;
  75
  76                 if m.valid = '1' then
  77                         if m.write_reg_enable = '1' then
  78                                 w_tmp.write_enable <= '1';
  79                                 w_tmp.write_reg <= m.write_reg_nr;
  80                                 w_tmp.write_data <= m.write_reg_data;
  81                         end if;
  82                         if m.write_cr_enable = '1' then
  83                                 c_tmp.write_cr_enable <= '1';
  84                                 c_tmp.write_cr_mask <= m.write_cr_mask;
  85                                 c_tmp.write_cr_data <= m.write_cr_data;
  86                         end if;
  87                 end if;
  88         end process;
  89 end;