writeback.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.crhelpers.all;
   8
   9 entity writeback is
  10     port (
  11         clk          : in std_ulogic;
  12
  13         e_in         : in Execute1ToWritebackType;
  14         l_in         : in DcacheToWritebackType;
  15
  16         w_out        : out WritebackToRegisterFileType;
  17         c_out        : out WritebackToCrFileType;
  18
  19         complete_out : out std_ulogic
  20         );
  21 end entity writeback;
  22
  23 architecture behaviour of writeback is
  24     subtype byte_index_t is unsigned(2 downto 0);
  25     type permutation_t is array(0 to 7) of byte_index_t;
  26     subtype byte_trim_t is std_ulogic_vector(1 downto 0);
  27     type trim_ctl_t is array(0 to 7) of byte_trim_t;
  28     type byte_sel_t is array(0 to 7) of std_ulogic;
  29
  30     signal data_len : unsigned(3 downto 0);
  31     signal data_in : std_ulogic_vector(63 downto 0);
  32     signal data_permuted : std_ulogic_vector(63 downto 0);
  33     signal data_trimmed : std_ulogic_vector(63 downto 0);
  34     signal data_latched : std_ulogic_vector(63 downto 0);
  35     signal perm : permutation_t;
  36     signal use_second : byte_sel_t;
  37     signal byte_offset : unsigned(2 downto 0);
  38     signal brev_lenm1 : unsigned(2 downto 0);
  39     signal trim_ctl : trim_ctl_t;
  40     signal rc : std_ulogic;
  41     signal partial_write : std_ulogic;
  42     signal sign_extend : std_ulogic;
  43     signal negative : std_ulogic;
  44     signal second_word : std_ulogic;
  45 begin
  46     writeback_0: process(clk)
  47     begin
  48         if rising_edge(clk) then
  49             if partial_write = '1' then
  50                 data_latched <= data_permuted;
  51             end if;
  52         end if;
  53     end process;
  54
  55     writeback_1: process(all)
  56         variable x : std_ulogic_vector(0 downto 0);
  57         variable y : std_ulogic_vector(0 downto 0);
  58         variable z : std_ulogic_vector(0 downto 0);
  59         variable w : std_ulogic_vector(0 downto 0);
  60         variable j : integer;
  61         variable k : unsigned(3 downto 0);
  62         variable cf: std_ulogic_vector(3 downto 0);
  63         variable xe: xer_common_t;
  64         variable zero : std_ulogic;
  65         variable sign : std_ulogic;
  66     begin
  67         x := "" & e_in.valid;
  68         y := "" & l_in.valid;
  69         assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
  70
  71         x := "" & e_in.write_enable;
  72         y := "" & l_in.write_enable;
  73         assert (to_integer(unsigned(x)) + to_integer(unsigned(y))) <= 1 severity failure;
  74
  75         w := "" & e_in.write_cr_enable;
  76         x := "" & (e_in.write_enable and e_in.rc);
  77         assert (to_integer(unsigned(w)) + to_integer(unsigned(x))) <= 1 severity failure;
  78
  79         w_out <= WritebackToRegisterFileInit;
  80         c_out <= WritebackToCrFileInit;
  81
  82         complete_out <= '0';
  83         if e_in.valid = '1' or l_in.valid = '1' then
  84             complete_out <= '1';
  85         end if;
  86
  87         rc <= '0';
  88         brev_lenm1 <= "000";
  89         partial_write <= '0';
  90         second_word <= '0';
  91         xe := e_in.xerc;
  92         data_in <= (others => '0');
  93
  94         if e_in.write_enable = '1' then
  95             w_out.write_reg <= e_in.write_reg;
  96             w_out.write_enable <= '1';
  97             rc <= e_in.rc;
  98         end if;
  99
 100         if e_in.write_cr_enable = '1' then
 101             c_out.write_cr_enable <= '1';
 102             c_out.write_cr_mask <= e_in.write_cr_mask;
 103             c_out.write_cr_data <= e_in.write_cr_data;
 104         end if;
 105
 106         if e_in.write_xerc_enable = '1' then
 107             c_out.write_xerc_enable <= '1';
 108             c_out.write_xerc_data <= e_in.xerc;
 109         end if;
 110
 111         sign_extend <= l_in.sign_extend;
 112         data_len <= unsigned(l_in.write_len);
 113         byte_offset <= unsigned(l_in.write_shift);
 114         if l_in.write_enable = '1' then
 115             w_out.write_reg <= gpr_to_gspr(l_in.write_reg);
 116             if l_in.byte_reverse = '1' then
 117                 brev_lenm1 <= unsigned(l_in.write_len(2 downto 0)) - 1;
 118             end if;
 119             w_out.write_enable <= '1';
 120             second_word <= l_in.second_word;
 121             if l_in.valid = '0' and (data_len + byte_offset > 8) then
 122                 partial_write <= '1';
 123             end if;
 124             xe := l_in.xerc;
 125         end if;
 126
 127         -- shift and byte-reverse data bytes
 128         for i in 0 to 7 loop
 129             k := ('0' & (to_unsigned(i, 3) xor brev_lenm1)) + ('0' & byte_offset);
 130             perm(i) <= k(2 downto 0);
 131             use_second(i) <= k(3);
 132         end loop;
 133         for i in 0 to 7 loop
 134             j := to_integer(perm(i)) * 8;
 135             data_permuted(i * 8 + 7 downto i * 8) <= l_in.write_data(j + 7 downto j);
 136         end loop;
 137
 138         -- If the data can arrive split over two cycles, this will be correct
 139         -- provided we don't have both sign extension and byte reversal.
 140         negative <= (data_len(3) and data_permuted(63)) or
 141                     (data_len(2) and data_permuted(31)) or
 142                     (data_len(1) and data_permuted(15)) or
 143                     (data_len(0) and data_permuted(7));
 144
 145         -- trim and sign-extend
 146         for i in 0 to 7 loop
 147             if i < to_integer(data_len) then
 148                 if second_word = '1' then
 149                     trim_ctl(i) <= '1' & not use_second(i);
 150                 else
 151                     trim_ctl(i) <= not use_second(i) & '0';
 152                 end if;
 153             else
 154                 trim_ctl(i) <= '0' & (negative and sign_extend);
 155             end if;
 156         end loop;
 157         for i in 0 to 7 loop
 158             case trim_ctl(i) is
 159                 when "11" =>
 160                     data_trimmed(i * 8 + 7 downto i * 8) <= data_latched(i * 8 + 7 downto i * 8);
 161                 when "10" =>
 162                     data_trimmed(i * 8 + 7 downto i * 8) <= data_permuted(i * 8 + 7 downto i * 8);
 163                 when "01" =>
 164                     data_trimmed(i * 8 + 7 downto i * 8) <= x"FF";
 165                 when others =>
 166                     data_trimmed(i * 8 + 7 downto i * 8) <= x"00";
 167             end case;
 168         end loop;
 169
 170         -- deliver to regfile
 171         if l_in.write_enable = '1' then
 172             w_out.write_data <= data_trimmed;
 173         else
 174             w_out.write_data <= e_in.write_data;
 175         end if;
 176
 177         -- Perform CR0 update for RC forms
 178         -- Note that loads never have a form with an RC bit, therefore this can test e_in.write_data
 179         if rc = '1' then
 180             sign := e_in.write_data(63);
 181             zero := not (or e_in.write_data);
 182             c_out.write_cr_enable <= '1';
 183             c_out.write_cr_mask <= num_to_fxm(0);
 184             cf(3) := sign;
 185             cf(2) := not sign and not zero;
 186             cf(1) := zero;
 187             cf(0) := xe.so;
 188             c_out.write_cr_data(31 downto 28) <= cf;
 189         end if;
 190     end process;
 191 end;