writeback.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.crhelpers.all;
   8
   9 entity writeback is
  10     port (
  11         clk          : in std_ulogic;
  12
  13         e_in         : in Execute1ToWritebackType;
  14         l_in         : in DcacheToWritebackType;
  15         m_in         : in MultiplyToWritebackType;
  16         d_in         : in DividerToWritebackType;
  17
  18         w_out        : out WritebackToRegisterFileType;
  19         c_out        : out WritebackToCrFileType;
  20
  21         complete_out : out std_ulogic
  22         );
  23 end entity writeback;
  24
  25 architecture behaviour of writeback is
  26     subtype byte_index_t is unsigned(2 downto 0);
  27     type permutation_t is array(0 to 7) of byte_index_t;
  28     subtype byte_trim_t is std_ulogic_vector(1 downto 0);
  29     type trim_ctl_t is array(0 to 7) of byte_trim_t;
  30     type byte_sel_t is array(0 to 7) of std_ulogic;
  31
  32     signal data_len : unsigned(3 downto 0);
  33     signal data_in : std_ulogic_vector(63 downto 0);
  34     signal data_permuted : std_ulogic_vector(63 downto 0);
  35     signal data_trimmed : std_ulogic_vector(63 downto 0);
  36     signal data_latched : std_ulogic_vector(63 downto 0);
  37     signal perm : permutation_t;
  38     signal use_second : byte_sel_t;
  39     signal byte_offset : unsigned(2 downto 0);
  40     signal brev_lenm1 : unsigned(2 downto 0);
  41     signal trim_ctl : trim_ctl_t;
  42     signal rc : std_ulogic;
  43     signal partial_write : std_ulogic;
  44     signal sign_extend : std_ulogic;
  45     signal negative : std_ulogic;
  46     signal second_word : std_ulogic;
  47     signal zero : std_ulogic;
  48 begin
  49     writeback_0: process(clk)
  50     begin
  51         if rising_edge(clk) then
  52             if partial_write = '1' then
  53                 data_latched <= data_permuted;
  54             end if;
  55         end if;
  56     end process;
  57
  58     writeback_1: process(all)
  59         variable x : std_ulogic_vector(0 downto 0);
  60         variable y : std_ulogic_vector(0 downto 0);
  61         variable z : std_ulogic_vector(0 downto 0);
  62         variable w : std_ulogic_vector(0 downto 0);
  63         variable j : integer;
  64         variable k : unsigned(3 downto 0);
  65         variable cf: std_ulogic_vector(3 downto 0);
  66         variable xe: xer_common_t;
  67     begin
  68         x := "" & e_in.valid;
  69         y := "" & l_in.valid;
  70         z := "" & m_in.valid;
  71         w := "" & d_in.valid;
  72         assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z)) + to_integer(unsigned(w))) <= 1 severity failure;
  73
  74         x := "" & e_in.write_enable;
  75         y := "" & l_in.write_enable;
  76         z := "" & m_in.write_reg_enable;
  77         w := "" & d_in.write_reg_enable;
  78         assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z)) + to_integer(unsigned(w))) <= 1 severity failure;
  79
  80         w := "" & e_in.write_cr_enable;
  81         x := "" & (e_in.write_enable and e_in.rc);
  82         y := "" & (m_in.valid and m_in.rc);
  83         z := "" & (d_in.valid and d_in.rc);
  84         assert (to_integer(unsigned(w)) + to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;
  85
  86         x := "" & e_in.write_xerc_enable;
  87         y := "" & m_in.write_xerc_enable;
  88         z := "" & D_in.write_xerc_enable;
  89         assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;
  90
  91         w_out <= WritebackToRegisterFileInit;
  92         c_out <= WritebackToCrFileInit;
  93
  94         complete_out <= '0';
  95         if e_in.valid = '1' or l_in.valid = '1' or m_in.valid = '1' or d_in.valid = '1' then
  96             complete_out <= '1';
  97         end if;
  98
  99         rc <= '0';
 100         brev_lenm1 <= "000";
 101         byte_offset <= "000";
 102         data_len <= x"8";
 103         partial_write <= '0';
 104         sign_extend <= '0';
 105         second_word <= '0';
 106         xe := e_in.xerc;
 107         data_in <= (others => '0');
 108
 109         if e_in.write_enable = '1' then
 110             w_out.write_reg <= e_in.write_reg;
 111             w_out.write_enable <= '1';
 112             data_in <= e_in.write_data;
 113             data_len <= unsigned(e_in.write_len);
 114             sign_extend <= e_in.sign_extend;
 115             rc <= e_in.rc;
 116         end if;
 117
 118         if e_in.write_cr_enable = '1' then
 119             c_out.write_cr_enable <= '1';
 120             c_out.write_cr_mask <= e_in.write_cr_mask;
 121             c_out.write_cr_data <= e_in.write_cr_data;
 122         end if;
 123
 124         if e_in.write_xerc_enable = '1' then
 125             c_out.write_xerc_enable <= '1';
 126             c_out.write_xerc_data <= e_in.xerc;
 127         end if;
 128
 129         if l_in.write_enable = '1' then
 130             w_out.write_reg <= gpr_to_gspr(l_in.write_reg);
 131             data_in <= l_in.write_data;
 132             data_len <= unsigned(l_in.write_len);
 133             byte_offset <= unsigned(l_in.write_shift);
 134             sign_extend <= l_in.sign_extend;
 135             if l_in.byte_reverse = '1' then
 136                 brev_lenm1 <= unsigned(l_in.write_len(2 downto 0)) - 1;
 137             end if;
 138             w_out.write_enable <= '1';
 139             second_word <= l_in.second_word;
 140             if l_in.valid = '0' and (data_len + byte_offset > 8) then
 141                 partial_write <= '1';
 142             end if;
 143             xe := l_in.xerc;
 144         end if;
 145
 146         if m_in.write_reg_enable = '1' then
 147             w_out.write_enable <= '1';
 148             w_out.write_reg <= gpr_to_gspr(m_in.write_reg_nr);
 149             data_in <= m_in.write_reg_data;
 150             rc <= m_in.rc;
 151             xe := m_in.xerc;
 152         end if;
 153
 154         if m_in.write_xerc_enable = '1' then
 155             c_out.write_xerc_enable <= '1';
 156             c_out.write_xerc_data <= m_in.xerc;
 157         end if;
 158
 159         if d_in.write_reg_enable = '1' then
 160             w_out.write_enable <= '1';
 161             w_out.write_reg <= gpr_to_gspr(d_in.write_reg_nr);
 162             data_in <= d_in.write_reg_data;
 163             rc <= d_in.rc;
 164             xe := d_in.xerc;
 165         end if;
 166
 167         if d_in.write_xerc_enable = '1' then
 168             c_out.write_xerc_enable <= '1';
 169             c_out.write_xerc_data <= d_in.xerc;
 170         end if;
 171
 172         -- shift and byte-reverse data bytes
 173         for i in 0 to 7 loop
 174             k := ('0' & (to_unsigned(i, 3) xor brev_lenm1)) + ('0' & byte_offset);
 175             perm(i) <= k(2 downto 0);
 176             use_second(i) <= k(3);
 177         end loop;
 178         for i in 0 to 7 loop
 179             j := to_integer(perm(i)) * 8;
 180             data_permuted(i * 8 + 7 downto i * 8) <= data_in(j + 7 downto j);
 181         end loop;
 182
 183         -- If the data can arrive split over two cycles, this will be correct
 184         -- provided we don't have both sign extension and byte reversal.
 185         negative <= (data_len(3) and data_permuted(63)) or
 186                     (data_len(2) and data_permuted(31)) or
 187                     (data_len(1) and data_permuted(15)) or
 188                     (data_len(0) and data_permuted(7));
 189
 190         -- trim and sign-extend
 191         for i in 0 to 7 loop
 192             if i < to_integer(data_len) then
 193                 if second_word = '1' then
 194                     trim_ctl(i) <= '1' & not use_second(i);
 195                 else
 196                     trim_ctl(i) <= not use_second(i) & '0';
 197                 end if;
 198             else
 199                 trim_ctl(i) <= '0' & (negative and sign_extend);
 200             end if;
 201         end loop;
 202         zero <= not negative;
 203         for i in 0 to 7 loop
 204             case trim_ctl(i) is
 205                 when "11" =>
 206                     data_trimmed(i * 8 + 7 downto i * 8) <= data_latched(i * 8 + 7 downto i * 8);
 207                 when "10" =>
 208                     data_trimmed(i * 8 + 7 downto i * 8) <= data_permuted(i * 8 + 7 downto i * 8);
 209                     if or data_permuted(i * 8 + 7 downto i * 8) /= '0' then
 210                         zero <= '0';
 211                     end if;
 212                 when "01" =>
 213                     data_trimmed(i * 8 + 7 downto i * 8) <= x"FF";
 214                 when others =>
 215                     data_trimmed(i * 8 + 7 downto i * 8) <= x"00";
 216             end case;
 217         end loop;
 218
 219         -- deliver to regfile
 220         w_out.write_data <= data_trimmed;
 221
 222         -- Perform CR0 update for RC forms
 223         if rc = '1' then
 224             c_out.write_cr_enable <= '1';
 225             c_out.write_cr_mask <= num_to_fxm(0);
 226             cf(3) := negative;
 227             cf(2) := not negative and not zero;
 228             cf(1) := zero;
 229             cf(0) := xe.so;
 230             c_out.write_cr_data(31 downto 28) <= cf;
 231         end if;
 232     end process;
 233 end;