2 use ieee.std_logic_1164.all;
11 w_in : in Execute2ToWritebackType;
12 l_in : in Loadstore2ToWritebackType;
13 m_in : in MultiplyToWritebackType;
15 w_out : out WritebackToRegisterFileType;
16 c_out : out WritebackToCrFileType;
18 complete_out : out std_ulogic
22 architecture behaviour of writeback is
23 signal w : Execute2ToWritebackType;
24 signal l : Loadstore2ToWritebackType;
25 signal m : MultiplyToWritebackType;
26 signal w_tmp : WritebackToRegisterFileType;
27 signal c_tmp : WritebackToCrFileType;
29 writeback_0: process(clk)
31 if rising_edge(clk) then
41 complete_out <= '1' when w.valid or l.valid or m.valid else '0';
43 writeback_1: process(all)
45 --assert (unsigned(w.valid) + unsigned(l.valid) + unsigned(m.valid)) <= 1;
46 --assert not(w.write_enable = '1' and l.write_enable = '1');
48 w_tmp <= WritebackToRegisterFileInit;
49 c_tmp <= WritebackToCrFileInit;
52 if w.write_enable = '1' then
53 w_tmp.write_reg <= w.write_reg;
54 w_tmp.write_data <= w.write_data;
55 w_tmp.write_enable <= '1';
58 if w.write_cr_enable = '1' then
60 c_tmp.write_cr_enable <= '1';
61 c_tmp.write_cr_mask <= w.write_cr_mask;
62 c_tmp.write_cr_data <= w.write_cr_data;
66 if l.valid = '1' and l.write_enable = '1' then
67 w_tmp.write_reg <= l.write_reg;
68 w_tmp.write_data <= l.write_data;
69 w_tmp.write_enable <= '1';
71 if l.valid = '1' and l.write_enable2 = '1' then
72 w_tmp.write_reg2 <= l.write_reg2;
73 w_tmp.write_data2 <= l.write_data2;
74 w_tmp.write_enable2 <= '1';
78 if m.write_reg_enable = '1' then
79 w_tmp.write_enable <= '1';
80 w_tmp.write_reg <= m.write_reg_nr;
81 w_tmp.write_data <= m.write_reg_data;
83 if m.write_cr_enable = '1' then
85 c_tmp.write_cr_enable <= '1';
86 c_tmp.write_cr_mask <= m.write_cr_mask;
87 c_tmp.write_cr_data <= m.write_cr_data;