writeback.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.crhelpers.all;
   8
   9 entity writeback is
  10     port (
  11         clk          : in std_ulogic;
  12
  13         e_in         : in Execute1ToWritebackType;
  14         l_in         : in Loadstore2ToWritebackType;
  15         m_in         : in MultiplyToWritebackType;
  16         d_in         : in DividerToWritebackType;
  17
  18         w_out        : out WritebackToRegisterFileType;
  19         c_out        : out WritebackToCrFileType;
  20
  21         complete_out : out std_ulogic
  22         );
  23 end entity writeback;
  24
  25 architecture behaviour of writeback is
  26     subtype byte_index_t is unsigned(2 downto 0);
  27     type permutation_t is array(0 to 7) of byte_index_t;
  28     subtype byte_trim_t is std_ulogic_vector(1 downto 0);
  29     type trim_ctl_t is array(0 to 7) of byte_trim_t;
  30     type byte_sel_t is array(0 to 7) of std_ulogic;
  31
  32     signal data_len : unsigned(3 downto 0);
  33     signal data_in : std_ulogic_vector(63 downto 0);
  34     signal data_permuted : std_ulogic_vector(63 downto 0);
  35     signal data_trimmed : std_ulogic_vector(63 downto 0);
  36     signal data_latched : std_ulogic_vector(63 downto 0);
  37     signal perm : permutation_t;
  38     signal use_second : byte_sel_t;
  39     signal byte_offset : unsigned(2 downto 0);
  40     signal brev_lenm1 : unsigned(2 downto 0);
  41     signal trim_ctl : trim_ctl_t;
  42     signal rc : std_ulogic;
  43     signal partial_write : std_ulogic;
  44     signal sign_extend : std_ulogic;
  45     signal negative : std_ulogic;
  46     signal second_word : std_ulogic;
  47 begin
  48     writeback_0: process(clk)
  49     begin
  50         if rising_edge(clk) then
  51             if partial_write = '1' then
  52                 data_latched <= data_permuted;
  53             end if;
  54         end if;
  55     end process;
  56
  57     writeback_1: process(all)
  58         variable x : std_ulogic_vector(0 downto 0);
  59         variable y : std_ulogic_vector(0 downto 0);
  60         variable z : std_ulogic_vector(0 downto 0);
  61         variable w : std_ulogic_vector(0 downto 0);
  62         variable j : integer;
  63         variable k : unsigned(3 downto 0);
  64     begin
  65         x := "" & e_in.valid;
  66         y := "" & l_in.valid;
  67         z := "" & m_in.valid;
  68         w := "" & d_in.valid;
  69         assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z)) + to_integer(unsigned(w))) <= 1 severity failure;
  70
  71         x := "" & e_in.write_enable;
  72         y := "" & l_in.write_enable;
  73         z := "" & m_in.write_reg_enable;
  74         w := "" & d_in.write_reg_enable;
  75         assert (to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z)) + to_integer(unsigned(w))) <= 1 severity failure;
  76
  77         w := "" & e_in.write_cr_enable;
  78         x := "" & (e_in.write_enable and e_in.rc);
  79         y := "" & (m_in.valid and m_in.rc);
  80         z := "" & (d_in.valid and d_in.rc);
  81         assert (to_integer(unsigned(w)) + to_integer(unsigned(x)) + to_integer(unsigned(y)) + to_integer(unsigned(z))) <= 1 severity failure;
  82
  83         w_out <= WritebackToRegisterFileInit;
  84         c_out <= WritebackToCrFileInit;
  85
  86         complete_out <= '0';
  87         if e_in.valid = '1' or l_in.valid = '1' or m_in.valid = '1' or d_in.valid = '1' then
  88             complete_out <= '1';
  89         end if;
  90
  91         rc <= '0';
  92         brev_lenm1 <= "000";
  93         byte_offset <= "000";
  94         data_len <= x"8";
  95         partial_write <= '0';
  96         sign_extend <= '0';
  97         second_word <= '0';
  98
  99         if e_in.write_enable = '1' then
 100             w_out.write_reg <= e_in.write_reg;
 101             data_in <= e_in.write_data;
 102             w_out.write_enable <= '1';
 103             data_len <= unsigned(e_in.write_len);
 104             sign_extend <= e_in.sign_extend;
 105             rc <= e_in.rc;
 106         end if;
 107
 108         if e_in.write_cr_enable = '1' then
 109             c_out.write_cr_enable <= '1';
 110             c_out.write_cr_mask <= e_in.write_cr_mask;
 111             c_out.write_cr_data <= e_in.write_cr_data;
 112         end if;
 113
 114         if l_in.write_enable = '1' then
 115             w_out.write_reg <= l_in.write_reg;
 116             data_in <= l_in.write_data;
 117             data_len <= unsigned(l_in.write_len);
 118             byte_offset <= unsigned(l_in.write_shift);
 119             sign_extend <= l_in.sign_extend;
 120             if l_in.byte_reverse = '1' then
 121                 brev_lenm1 <= unsigned(l_in.write_len(2 downto 0)) - 1;
 122             end if;
 123             w_out.write_enable <= '1';
 124             second_word <= l_in.second_word;
 125             if l_in.valid = '0' and (data_len + byte_offset > 8) then
 126                 partial_write <= '1';
 127             end if;
 128         end if;
 129
 130         if m_in.write_reg_enable = '1' then
 131             w_out.write_enable <= '1';
 132             w_out.write_reg <= m_in.write_reg_nr;
 133             data_in <= m_in.write_reg_data;
 134             rc <= m_in.rc;
 135         end if;
 136
 137         if d_in.write_reg_enable = '1' then
 138             w_out.write_enable <= '1';
 139             w_out.write_reg <= d_in.write_reg_nr;
 140             data_in <= d_in.write_reg_data;
 141             rc <= d_in.rc;
 142         end if;
 143
 144         -- shift and byte-reverse data bytes
 145         for i in 0 to 7 loop
 146             k := ('0' & (to_unsigned(i, 3) xor brev_lenm1)) + ('0' & byte_offset);
 147             perm(i) <= k(2 downto 0);
 148             use_second(i) <= k(3);
 149         end loop;
 150         for i in 0 to 7 loop
 151             j := to_integer(perm(i)) * 8;
 152             data_permuted(i * 8 + 7 downto i * 8) <= data_in(j + 7 downto j);
 153         end loop;
 154
 155         -- If the data can arrive split over two cycles, this will be correct
 156         -- provided we don't have both sign extension and byte reversal.
 157         negative <= (data_len(2) and data_permuted(31)) or (data_len(1) and data_permuted(15)) or
 158                     (data_len(0) and data_permuted(7));
 159
 160         -- trim and sign-extend
 161         for i in 0 to 7 loop
 162             if i < to_integer(data_len) then
 163                 if second_word = '1' then
 164                     trim_ctl(i) <= '1' & not use_second(i);
 165                 else
 166                     trim_ctl(i) <= not use_second(i) & '0';
 167                 end if;
 168             else
 169                 trim_ctl(i) <= '0' & (negative and sign_extend);
 170             end if;
 171         end loop;
 172         for i in 0 to 7 loop
 173             case trim_ctl(i) is
 174                 when "11" =>
 175                     data_trimmed(i * 8 + 7 downto i * 8) <= data_latched(i * 8 + 7 downto i * 8);
 176                 when "10" =>
 177                     data_trimmed(i * 8 + 7 downto i * 8) <= data_permuted(i * 8 + 7 downto i * 8);
 178                 when "01" =>
 179                     data_trimmed(i * 8 + 7 downto i * 8) <= x"FF";
 180                 when others =>
 181                     data_trimmed(i * 8 + 7 downto i * 8) <= x"00";
 182             end case;
 183         end loop;
 184
 185         -- deliver to regfile
 186         w_out.write_data <= data_trimmed;
 187
 188         -- test value against 0 and set CR0 if requested
 189         if rc = '1' then
 190             c_out.write_cr_enable <= '1';
 191             c_out.write_cr_mask <= num_to_fxm(0);
 192             if data_trimmed(63) = '1' then
 193                 c_out.write_cr_data <= x"80000000";
 194             elsif or (data_trimmed(62 downto 0)) = '1' then
 195                 c_out.write_cr_data <= x"40000000";
 196             else
 197                 c_out.write_cr_data <= x"20000000";
 198             end if;
 199         end if;
 200     end process;
 201 end;