2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
9 use unisim.vcomponents.all;
15 m_in : in MultiplyInputType;
16 m_out : out MultiplyOutputType
20 architecture behaviour of multiply is
21 signal m00_p, m01_p, m02_p, m03_p : std_ulogic_vector(47 downto 0);
22 signal m00_pc : std_ulogic_vector(47 downto 0);
23 signal m10_p, m11_p, m12_p, m13_p : std_ulogic_vector(47 downto 0);
24 signal m11_pc, m12_pc, m13_pc : std_ulogic_vector(47 downto 0);
25 signal m20_p, m21_p, m22_p, m23_p : std_ulogic_vector(47 downto 0);
26 signal s0_pc, s1_pc : std_ulogic_vector(47 downto 0);
27 signal product_lo : std_ulogic_vector(31 downto 0);
28 signal product : std_ulogic_vector(127 downto 0);
29 signal addend : std_ulogic_vector(127 downto 0);
30 signal s0_carry, p0_carry : std_ulogic_vector(3 downto 0);
31 signal p0_mask : std_ulogic_vector(47 downto 0);
32 signal p0_pat, p0_patb : std_ulogic;
33 signal p1_pat, p1_patb : std_ulogic;
35 signal req_32bit, r32_1 : std_ulogic;
36 signal req_not, rnot_1 : std_ulogic;
37 signal valid_1 : std_ulogic;
38 signal overflow, ovf_in : std_ulogic;
41 addend <= m_in.addend;
57 A => "0000000" & m_in.data1(22 downto 0),
58 ACIN => (others => '0'),
60 B => '0' & m_in.data2(16 downto 0),
61 BCIN => (others => '0'),
62 C => "00000000000000" & addend(33 downto 0),
85 PCIN => (others => '0'),
113 A => "0000000" & m_in.data1(22 downto 0),
114 ACIN => (others => '0'),
116 B => '0' & m_in.data2(33 downto 17),
117 BCIN => (others => '0'),
118 C => (others => '0'),
136 D => (others => '0'),
143 RSTALLCARRYIN => '0',
168 A => "0000000" & m_in.data1(22 downto 0),
169 ACIN => (others => '0'),
171 B => '0' & m_in.data2(50 downto 34),
172 BCIN => (others => '0'),
173 C => x"0000000" & "000" & addend(50 downto 34),
191 D => (others => '0'),
196 PCIN => (others => '0'),
198 RSTALLCARRYIN => '0',
223 A => "0000000" & m_in.data1(22 downto 0),
224 ACIN => (others => '0'),
226 B => "00000" & m_in.data2(63 downto 51),
227 BCIN => (others => '0'),
228 C => x"000000" & '0' & addend(73 downto 51),
246 D => (others => '0'),
251 PCIN => (others => '0'),
253 RSTALLCARRYIN => '0',
279 A => "0000000000000" & m_in.data1(39 downto 23),
280 ACIN => (others => '0'),
282 B => '0' & m_in.data2(16 downto 0),
283 BCIN => (others => '0'),
284 C => x"000" & "00" & m01_p(39 downto 6),
302 D => (others => '0'),
307 PCIN => (others => '0'),
309 RSTALLCARRYIN => '0',
335 A => "0000000000000" & m_in.data1(39 downto 23),
336 ACIN => (others => '0'),
338 B => '0' & m_in.data2(33 downto 17),
339 BCIN => (others => '0'),
340 C => x"000" & "00" & m02_p(39 downto 6),
358 D => (others => '0'),
363 PCIN => (others => '0'),
366 RSTALLCARRYIN => '0',
392 A => "0000000000000" & m_in.data1(39 downto 23),
393 ACIN => (others => '0'),
395 B => '0' & m_in.data2(50 downto 34),
396 BCIN => (others => '0'),
397 C => x"0000" & '0' & m03_p(36 downto 6),
415 D => (others => '0'),
420 PCIN => (others => '0'),
423 RSTALLCARRYIN => '0',
448 A => "0000000000000" & m_in.data1(39 downto 23),
449 ACIN => (others => '0'),
451 B => "00000" & m_in.data2(63 downto 51),
452 BCIN => (others => '0'),
453 C => x"0000000" & "000" & addend(90 downto 74),
471 D => (others => '0'),
476 PCIN => (others => '0'),
479 RSTALLCARRYIN => '0',
504 A => "000000" & m_in.data1(63 downto 40),
505 ACIN => (others => '0'),
507 B => '0' & m_in.data2(16 downto 0),
508 BCIN => (others => '0'),
509 C => (others => '0'),
527 D => (others => '0'),
534 RSTALLCARRYIN => '0',
559 A => "000000" & m_in.data1(63 downto 40),
560 ACIN => (others => '0'),
562 B => '0' & m_in.data2(33 downto 17),
563 BCIN => (others => '0'),
564 C => (others => '0'),
582 D => (others => '0'),
589 RSTALLCARRYIN => '0',
614 A => "000000" & m_in.data1(63 downto 40),
615 ACIN => (others => '0'),
617 B => '0' & m_in.data2(50 downto 34),
618 BCIN => (others => '0'),
619 C => (others => '0'),
637 D => (others => '0'),
644 RSTALLCARRYIN => '0',
669 A => "000000" & m_in.data1(63 downto 40),
670 ACIN => (others => '0'),
672 B => "00000" & m_in.data2(63 downto 51),
673 BCIN => (others => '0'),
674 C => x"00" & "000" & addend(127 downto 91),
692 D => (others => '0'),
697 PCIN => (others => '0'),
699 RSTALLCARRYIN => '0',
727 A => m22_p(5 downto 0) & x"0000" & m10_p(34 downto 27),
728 ACIN => (others => '0'),
730 B => m10_p(26 downto 9),
731 BCIN => (others => '0'),
732 C => m20_p(39 downto 0) & m02_p(5 downto 0) & "00",
736 CARRYOUT => s0_carry,
751 D => (others => '0'),
755 PCIN => (others => '0'),
758 RSTALLCARRYIN => '0',
786 A => x"000" & m22_p(41 downto 24),
787 ACIN => (others => '0'),
789 B => m22_p(23 downto 6),
790 BCIN => (others => '0'),
791 C => m23_p(36 downto 0) & x"00" & "0" & m20_p(41 downto 40),
793 CARRYIN => s0_carry(3),
809 D => (others => '0'),
813 PCIN => (others => '0'),
816 RSTALLCARRYIN => '0',
827 -- mask is 0 for 32-bit ops, 0x0000ffffffff for 64-bit
828 p0_mask(47 downto 31) <= (others => '0');
829 p0_mask(30 downto 0) <= (others => not r32_1);
847 USE_PATTERN_DETECT => "PATDET"
850 A => m21_p(22 downto 0) & m03_p(5 downto 0) & '0',
851 ACIN => (others => '0'),
852 ALUMODE => "00" & rnot_1 & '0',
853 B => (others => '0'),
854 BCIN => (others => '0'),
859 CARRYOUT => p0_carry,
863 CEALUMODE => valid_1,
874 D => (others => '0'),
878 P => product(79 downto 32),
879 PATTERNDETECT => p0_pat,
880 PATTERNBDETECT => p0_patb,
883 RSTALLCARRYIN => '0',
905 MASK => x"000000000000",
910 USE_PATTERN_DETECT => "PATDET"
913 A => x"0000000" & '0' & m21_p(41),
914 ACIN => (others => '0'),
915 ALUMODE => "00" & rnot_1 & '0',
916 B => m21_p(40 downto 23),
917 BCIN => (others => '0'),
918 C => (others => '0'),
920 CARRYIN => p0_carry(3),
925 CEALUMODE => valid_1,
936 D => (others => '0'),
940 P => product(127 downto 80),
941 PATTERNDETECT => p1_pat,
942 PATTERNBDETECT => p1_patb,
945 RSTALLCARRYIN => '0',
956 product(31 downto 0) <= product_lo xor (31 downto 0 => req_not);
958 mult_out: process(all)
959 variable ov : std_ulogic;
961 -- set overflow if the high bits are neither all zeroes nor all ones
962 if req_32bit = '0' then
963 ov := not ((p1_pat and p0_pat) or (p1_patb and p0_patb));
965 ov := not ((p1_pat and p0_pat and not product(31)) or
966 (p1_patb and p0_patb and product(31)));
970 m_out.result <= product;
971 m_out.overflow <= overflow;
976 if rising_edge(clk) then
977 product_lo <= m10_p(8 downto 0) & m01_p(5 downto 0) & m00_p(16 downto 0);
978 m_out.valid <= valid_1;
979 valid_1 <= m_in.valid;
981 r32_1 <= m_in.is_32bit;
983 rnot_1 <= m_in.not_result;
988 end architecture behaviour;