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600f5129c90e3fdd72fa1e5720e8379e0f0c4504
[mesa.git] /
1 Reading src/freedreno/.gitlab-ci/traces/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.rd.gz...
2 gpu_id: 640
3 cmd: deqp-vk/74711: fence=247337
4 ############################################################
5 cmdstream: 265 dwords
6 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
7 { EVENT = CACHE_INVALIDATE }
8 event CACHE_INVALIDATE
9 0000000001058000: 0000: 70460001 00000031
10 t4 write HLSQ_INVALIDATE_CMD (bb08)
11 HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
12 0000000001058008: 0000: 40bb0801 000fffff
13 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
14 0000000001058010: 0000: 70268000
15 t4 write RB_CCU_CNTL (8e07)
16 RB_CCU_CNTL: { OFFSET = 0x20000 }
17 0000000001058014: 0000: 408e0701 10000000
18 t4 write RB_UNKNOWN_8E04 (8e04)
19 RB_UNKNOWN_8E04: 0x100000
20 000000000105801c: 0000: 408e0401 00100000
21 t4 write SP_UNKNOWN_AE04 (ae04)
22 SP_UNKNOWN_AE04: 0x8
23 0000000001058024: 0000: 48ae0401 00000008
24 t4 write SP_UNKNOWN_AE00 (ae00)
25 SP_UNKNOWN_AE00: 0
26 000000000105802c: 0000: 40ae0001 00000000
27 t4 write SP_UNKNOWN_AE0F (ae0f)
28 SP_UNKNOWN_AE0F: 0x3f
29 0000000001058034: 0000: 40ae0f01 0000003f
30 t4 write SP_UNKNOWN_B605 (b605)
31 SP_UNKNOWN_B605: 0x44
32 000000000105803c: 0000: 40b60501 00000044
33 t4 write SP_UNKNOWN_B600 (b600)
34 SP_UNKNOWN_B600: 0x100000
35 0000000001058044: 0000: 40b60001 00100000
36 t4 write HLSQ_UNKNOWN_BE00 (be00)
37 HLSQ_UNKNOWN_BE00: 0x80
38 000000000105804c: 0000: 48be0001 00000080
39 t4 write HLSQ_UNKNOWN_BE01 (be01)
40 HLSQ_UNKNOWN_BE01: 0
41 0000000001058054: 0000: 40be0101 00000000
42 t4 write VPC_UNKNOWN_9600 (9600)
43 VPC_UNKNOWN_9600: 0
44 000000000105805c: 0000: 48960001 00000000
45 t4 write GRAS_UNKNOWN_8600 (8600)
46 GRAS_UNKNOWN_8600: 0x880
47 0000000001058064: 0000: 40860001 00000880
48 t4 write HLSQ_UNKNOWN_BE04 (be04)
49 HLSQ_UNKNOWN_BE04: 0
50 000000000105806c: 0000: 40be0401 00000000
51 t4 write SP_UNKNOWN_AE03 (ae03)
52 SP_UNKNOWN_AE03: 0x410
53 0000000001058074: 0000: 40ae0301 00000410
54 t4 write SP_IBO_COUNT (ab20)
55 SP_IBO_COUNT: 0
56 000000000105807c: 0000: 48ab2001 00000000
57 t4 write SP_UNKNOWN_B182 (b182)
58 SP_UNKNOWN_B182: 0
59 0000000001058084: 0000: 48b18201 00000000
60 t4 write HLSQ_SHARED_CONSTS (bb11)
61 HLSQ_SHARED_CONSTS: { 0 }
62 000000000105808c: 0000: 48bb1101 00000000
63 t4 write UCHE_UNKNOWN_0E12 (0e12)
64 UCHE_UNKNOWN_0E12: 0x3200000
65 0000000001058094: 0000: 400e1201 03200000
66 t4 write UCHE_CLIENT_PF (0e19)
67 UCHE_CLIENT_PF: { PERFSEL = 0x4 }
68 000000000105809c: 0000: 480e1901 00000004
69 t4 write RB_UNKNOWN_8E01 (8e01)
70 RB_UNKNOWN_8E01: 0
71 00000000010580a4: 0000: 408e0101 00000000
72 t4 write SP_UNKNOWN_A982 (a982)
73 SP_UNKNOWN_A982: 0
74 00000000010580ac: 0000: 48a98201 00000000
75 t4 write SP_UNKNOWN_A9A8 (a9a8)
76 SP_UNKNOWN_A9A8: 0
77 00000000010580b4: 0000: 40a9a801 00000000
78 t4 write SP_MODE_CONTROL (ab00)
79 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
80 00000000010580bc: 0000: 40ab0001 00000005
81 t4 write VFD_ADD_OFFSET (a009)
82 VFD_ADD_OFFSET: { VERTEX }
83 00000000010580c4: 0000: 48a00901 00000001
84 t4 write RB_UNKNOWN_8811 (8811)
85 RB_UNKNOWN_8811: 0x1
86 00000000010580cc: 0000: 48881101 00000010
87 t4 write PC_MODE_CNTL (9804)
88 PC_MODE_CNTL: 0x1f
89 00000000010580d4: 0000: 48980401 0000001f
90 t4 write RB_SRGB_CNTL (880f)
91 RB_SRGB_CNTL: { 0 }
92 00000000010580dc: 0000: 48880f01 00000000
93 t4 write GRAS_UNKNOWN_8110 (8110)
94 GRAS_UNKNOWN_8110: 0
95 00000000010580e4: 0000: 40811001 00000000
96 t4 write RB_RENDER_CONTROL0 (8809)
97 RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 }
98 00000000010580ec: 0000: 48880901 00000401
99 t4 write RB_RENDER_CONTROL1 (880a)
100 RB_RENDER_CONTROL1: { 0 }
101 00000000010580f4: 0000: 48880a01 00000000
102 t4 write RB_FS_OUTPUT_CNTL0 (880b)
103 RB_FS_OUTPUT_CNTL0: { 0 }
104 00000000010580fc: 0000: 40880b01 00000000
105 t4 write RB_UNKNOWN_8818 (8818)
106 RB_UNKNOWN_8818: 0
107 0000000001058104: 0000: 48881801 00000000
108 t4 write RB_UNKNOWN_8819 (8819)
109 RB_UNKNOWN_8819: 0
110 000000000105810c: 0000: 40881901 00000000
111 t4 write RB_UNKNOWN_881A (881a)
112 RB_UNKNOWN_881A: 0
113 0000000001058114: 0000: 40881a01 00000000
114 t4 write RB_UNKNOWN_881B (881b)
115 RB_UNKNOWN_881B: 0
116 000000000105811c: 0000: 48881b01 00000000
117 t4 write RB_UNKNOWN_881C (881c)
118 RB_UNKNOWN_881C: 0
119 0000000001058124: 0000: 40881c01 00000000
120 t4 write RB_UNKNOWN_881D (881d)
121 RB_UNKNOWN_881D: 0
122 000000000105812c: 0000: 48881d01 00000000
123 t4 write RB_UNKNOWN_881E (881e)
124 RB_UNKNOWN_881E: 0
125 0000000001058134: 0000: 48881e01 00000000
126 t4 write RB_UNKNOWN_88F0 (88f0)
127 RB_UNKNOWN_88F0: 0
128 000000000105813c: 0000: 4888f001 00000000
129 t4 write VPC_UNKNOWN_9107 (9107)
130 VPC_UNKNOWN_9107: 0
131 0000000001058144: 0000: 48910701 00000000
132 t4 write VPC_POINT_COORD_INVERT (9236)
133 VPC_POINT_COORD_INVERT: { 0 }
134 000000000105814c: 0000: 40923601 00000000
135 t4 write VPC_UNKNOWN_9300 (9300)
136 VPC_UNKNOWN_9300: 0
137 0000000001058154: 0000: 48930001 00000000
138 t4 write VPC_SO_DISABLE (9306)
139 VPC_SO_DISABLE: { DISABLE }
140 000000000105815c: 0000: 48930601 00000001
141 t4 write PC_UNKNOWN_9980 (9980)
142 PC_UNKNOWN_9980: 0
143 0000000001058164: 0000: 40998001 00000000
144 t4 write PC_PRIMITIVE_CNTL_6 (9b06)
145 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
146 000000000105816c: 0000: 409b0601 00000000
147 t4 write PC_UNKNOWN_9B07 (9b07)
148 PC_UNKNOWN_9B07: 0
149 0000000001058174: 0000: 489b0701 00000000
150 t4 write SP_UNKNOWN_A81B (a81b)
151 SP_UNKNOWN_A81B: 0
152 000000000105817c: 0000: 40a81b01 00000000
153 t4 write SP_UNKNOWN_B183 (b183)
154 SP_UNKNOWN_B183: 0
155 0000000001058184: 0000: 40b18301 00000000
156 t4 write GRAS_UNKNOWN_8099 (8099)
157 GRAS_UNKNOWN_8099: 0
158 000000000105818c: 0000: 40809901 00000000
159 t4 write GRAS_UNKNOWN_80A0 (80a0)
160 GRAS_UNKNOWN_80A0: 0x2
161 0000000001058194: 0000: 4080a001 00000002
162 t4 write GRAS_UNKNOWN_80AF (80af)
163 GRAS_UNKNOWN_80AF: FALSE
164 000000000105819c: 0000: 4080af01 00000000
165 t4 write VPC_UNKNOWN_9210 (9210)
166 VPC_UNKNOWN_9210: 0
167 00000000010581a4: 0000: 48921001 00000000
168 t4 write VPC_UNKNOWN_9211 (9211)
169 VPC_UNKNOWN_9211: 0
170 00000000010581ac: 0000: 40921101 00000000
171 t4 write VPC_UNKNOWN_9602 (9602)
172 VPC_UNKNOWN_9602: FALSE
173 00000000010581b4: 0000: 40960201 00000000
174 t4 write PC_UNKNOWN_9E72 (9e72)
175 PC_UNKNOWN_9E72: 0
176 00000000010581bc: 0000: 409e7201 00000000
177 t4 write SP_TP_UNKNOWN_B309 (b309)
178 SP_TP_UNKNOWN_B309: 0xa2
179 00000000010581c4: 0000: 40b30901 000000a2
180 t4 write HLSQ_CONTROL_5_REG (b986)
181 HLSQ_CONTROL_5_REG: 0xfc
182 00000000010581cc: 0000: 48b98601 000000fc
183 t4 write VFD_MODE_CNTL (a007)
184 VFD_MODE_CNTL: { 0 }
185 00000000010581d4: 0000: 40a00701 00000000
186 t4 write VFD_UNKNOWN_A008 (a008)
187 VFD_UNKNOWN_A008: 0
188 00000000010581dc: 0000: 40a00801 00000000
189 t4 write PC_MODE_CNTL (9804)
190 PC_MODE_CNTL: 0x1f
191 00000000010581e4: 0000: 48980401 0000001f
192 t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords)
193 { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
194 { ADDR_LO = 0 }
195 { ADDR_HI = 0 }
196 00000000010581ec: 0000: 70438003 00040000 00000000 00000000
197 t4 write SP_HS_CTRL_REG0 (a830)
198 SP_HS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS }
199 00000000010581fc: 0000: 40a83001 00000000
200 t4 write SP_GS_CTRL_REG0 (a870)
201 SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS }
202 0000000001058204: 0000: 48a87001 00000000
203 t4 write GRAS_LRZ_CNTL (8100)
204 GRAS_LRZ_CNTL: { 0 }
205 000000000105820c: 0000: 48810001 00000000
206 t4 write RB_LRZ_CNTL (8898)
207 RB_LRZ_CNTL: { 0 }
208 0000000001058214: 0000: 40889801 00000000
209 t4 write SP_TP_BORDER_COLOR_BASE_ADDR (b302)
210 SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
211 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
212 000000000105821c: 0000: 48b30202 01011000 00000000
213 t4 write SP_PS_TP_BORDER_COLOR_BASE_ADDR (b180)
214 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
215 SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
216 0000000001058228: 0000: 40b18002 01011000 00000000
217 t4 write VSC_DRAW_STRM_SIZE_ADDRESS_LO (0c03)
218 VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x10fd000
219 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
220 0000000001058234: 0000: 480c0302 010fd000 00000000
221 t4 write VSC_PRIM_STRM_ADDRESS_LO (0c30)
222 VSC_PRIM_STRM_ADDRESS_LO: 0x105c000
223 VSC_PRIM_STRM_ADDRESS_HI: 0
224 0000000001058240: 0000: 480c3002 0105c000 00000000
225 t4 write VSC_DRAW_STRM_ADDRESS_LO (0c34)
226 VSC_DRAW_STRM_ADDRESS_LO: 0x10dc800
227 VSC_DRAW_STRM_ADDRESS_HI: 0
228 000000000105824c: 0000: 400c3402 010dc800 00000000
229 t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
230 { EVENT = PC_CCU_FLUSH_COLOR_TS }
231 { ADDR_0_LO = 0x1011880 }
232 { ADDR_0_HI = 0 }
233 { 3 = 0 }
234 event PC_CCU_FLUSH_COLOR_TS
235 0000000001058258: 0000: 70460004 0000001d 01011880 00000000 00000000
236 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
237 { EVENT = PC_CCU_INVALIDATE_COLOR }
238 event PC_CCU_INVALIDATE_COLOR
239 000000000105826c: 0000: 70460001 00000019
240 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
241 0000000001058274: 0000: 70268000
242 t4 write RB_2D_UNKNOWN_8C01 (8c01)
243 RB_2D_UNKNOWN_8C01: 0
244 0000000001058278: 0000: 488c0101 00000000
245 t4 write RB_2D_BLIT_CNTL (8c00)
246 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 }
247 0000000001058280: 0000: 408c0001 10f03080
248 t4 write GRAS_2D_BLIT_CNTL (8400)
249 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 }
250 0000000001058288: 0000: 48840001 10f03080
251 t4 write SP_2D_DST_FORMAT (acc0)
252 SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf }
253 0000000001058290: 0000: 48acc001 0000f180
254 t4 write RB_2D_SRC_SOLID_C0 (8c2c)
255 RB_2D_SRC_SOLID_C0: 0
256 RB_2D_SRC_SOLID_C1: 0
257 RB_2D_SRC_SOLID_C2: 0
258 RB_2D_SRC_SOLID_C3: 0xff
259 0000000001058298: 0000: 488c2c04 00000000 00000000 00000000 000000ff
260 t4 write GRAS_2D_DST_TL (8405)
261 GRAS_2D_DST_TL: { X = 0 | Y = 0 }
262 GRAS_2D_DST_BR: { X = 255 | Y = 255 }
263 00000000010582ac: 0000: 48840502 00000000 00ff00ff
264 t4 write RB_2D_DST_INFO (8c17)
265 RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
266 RB_2D_DST_LO: 0x1013000
267 RB_2D_DST_HI: 0
268 RB_2D_DST_PITCH: 1024
269 00000000010582b8: 0000: 408c1704 00001330 01013000 00000000 00000010
270 t4 write RB_2D_DST_FLAGS_LO (8c20)
271 RB_2D_DST_FLAGS_LO: 0x1012000
272 RB_2D_DST_FLAGS_HI: 0
273 RB_2D_DST_FLAGS_PITCH: 64 | 0x4000
274 00000000010582cc: 0000: 488c2083 01012000 00000000 00004001
275 t7 opcode: CP_BLIT (2c) (2 dwords)
276 { OP = BLIT_OP_SCALE }
277 mode: (null)
278 skip_ib2: g=0, l=0
279 draw[0] register values
280 !+ 010fd000 VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x10fd000
281 + 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
282 !+ 0105c000 VSC_PRIM_STRM_ADDRESS_LO: 0x105c000
283 + 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0
284 !+ 010dc800 VSC_DRAW_STRM_ADDRESS_LO: 0x10dc800
285 + 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0
286 !+ 03200000 UCHE_UNKNOWN_0E12: 0x3200000
287 !+ 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 }
288 + 00000000 GRAS_UNKNOWN_8099: 0
289 !+ 00000002 GRAS_UNKNOWN_80A0: 0x2
290 + 00000000 GRAS_UNKNOWN_80AF: FALSE
291 + 00000000 GRAS_LRZ_CNTL: { 0 }
292 + 00000000 GRAS_UNKNOWN_8110: 0
293 !+ 10f03080 GRAS_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 }
294 + 00000000 GRAS_2D_DST_TL: { X = 0 | Y = 0 }
295 !+ 00ff00ff GRAS_2D_DST_BR: { X = 255 | Y = 255 }
296 !+ 00000880 GRAS_UNKNOWN_8600: 0x880
297 !+ 00000401 RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 }
298 + 00000000 RB_RENDER_CONTROL1: { 0 }
299 + 00000000 RB_FS_OUTPUT_CNTL0: { 0 }
300 + 00000000 RB_SRGB_CNTL: { 0 }
301 !+ 00000010 RB_UNKNOWN_8811: 0x1
302 + 00000000 RB_UNKNOWN_8818: 0
303 + 00000000 RB_UNKNOWN_8819: 0
304 + 00000000 RB_UNKNOWN_881A: 0
305 + 00000000 RB_UNKNOWN_881B: 0
306 + 00000000 RB_UNKNOWN_881C: 0
307 + 00000000 RB_UNKNOWN_881D: 0
308 + 00000000 RB_UNKNOWN_881E: 0
309 + 00000000 RB_LRZ_CNTL: { 0 }
310 + 00000000 RB_UNKNOWN_88F0: 0
311 !+ 10f03080 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 }
312 + 00000000 RB_2D_UNKNOWN_8C01: 0
313 !+ 00001330 RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
314 !+ 01013000 RB_2D_DST_LO: 0x1013000
315 + 00000000 RB_2D_DST_HI: 0
316 !+ 00000010 RB_2D_DST_PITCH: 1024
317 !+ 01012000 RB_2D_DST_FLAGS_LO: 0x1012000
318 + 00000000 RB_2D_DST_FLAGS_HI: 0
319 !+ 00004001 RB_2D_DST_FLAGS_PITCH: 64 | 0x4000
320 + 00000000 RB_2D_SRC_SOLID_C0: 0
321 + 00000000 RB_2D_SRC_SOLID_C1: 0
322 + 00000000 RB_2D_SRC_SOLID_C2: 0
323 !+ 000000ff RB_2D_SRC_SOLID_C3: 0xff
324 + 00000000 RB_UNKNOWN_8E01: 0
325 !+ 00100000 RB_UNKNOWN_8E04: 0x100000
326 !+ 10000000 RB_CCU_CNTL: { OFFSET = 0x20000 }
327 + 00000000 VPC_UNKNOWN_9107: 0
328 + 00000000 VPC_UNKNOWN_9210: 0
329 + 00000000 VPC_UNKNOWN_9211: 0
330 + 00000000 VPC_POINT_COORD_INVERT: { 0 }
331 + 00000000 VPC_UNKNOWN_9300: 0
332 !+ 00000001 VPC_SO_DISABLE: { DISABLE }
333 + 00000000 VPC_UNKNOWN_9600: 0
334 + 00000000 VPC_UNKNOWN_9602: FALSE
335 !+ 0000001f PC_MODE_CNTL: 0x1f
336 + 00000000 PC_UNKNOWN_9980: 0
337 + 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 }
338 + 00000000 PC_UNKNOWN_9B07: 0
339 + 00000000 PC_UNKNOWN_9E72: 0
340 + 00000000 VFD_MODE_CNTL: { 0 }
341 + 00000000 VFD_UNKNOWN_A008: 0
342 !+ 00000001 VFD_ADD_OFFSET: { VERTEX }
343 + 00000000 SP_UNKNOWN_A81B: 0
344 + 00000000 SP_HS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS }
345 + 00000000 SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS }
346 + 00000000 SP_UNKNOWN_A982: 0
347 + 00000000 SP_UNKNOWN_A9A8: 0
348 !+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
349 + 00000000 SP_IBO_COUNT: 0
350 !+ 0000f180 SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf }
351 + 00000000 SP_UNKNOWN_AE00: 0
352 !+ 00000410 SP_UNKNOWN_AE03: 0x410
353 !+ 00000008 SP_UNKNOWN_AE04: 0x8
354 !+ 0000003f SP_UNKNOWN_AE0F: 0x3f
355 !+ 01011000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
356 + 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
357 + 00000000 SP_UNKNOWN_B182: 0
358 + 00000000 SP_UNKNOWN_B183: 0
359 !+ 01011000 SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
360 + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
361 !+ 000000a2 SP_TP_UNKNOWN_B309: 0xa2
362 !+ 00100000 SP_UNKNOWN_B600: 0x100000
363 !+ 00000044 SP_UNKNOWN_B605: 0x44
364 !+ 000000fc HLSQ_CONTROL_5_REG: 0xfc
365 !+ 000fffff HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | CS_STATE | CS_IBO | GFX_IBO | CS_SHARED_CONST | GFX_SHARED_CONST | CS_BINDLESS = 0x1f | GFX_BINDLESS = 0x1f }
366 + 00000000 HLSQ_SHARED_CONSTS: { 0 }
367 !+ 00000080 HLSQ_UNKNOWN_BE00: 0x80
368 + 00000000 HLSQ_UNKNOWN_BE01: 0
369 + 00000000 HLSQ_UNKNOWN_BE04: 0
370 00000000010582dc: 0000: 702c0001 00000003
371 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
372 { EVENT = LRZ_FLUSH }
373 event LRZ_FLUSH
374 00000000010582e4: 0000: 70460001 00000026
375 t7 opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
376 00000000010582ec: 0000: 709d0001 00000000
377 t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
378 { EVENT = PC_CCU_FLUSH_COLOR_TS }
379 { ADDR_0_LO = 0x1011880 }
380 { ADDR_0_HI = 0 }
381 { 3 = 0 }
382 event PC_CCU_FLUSH_COLOR_TS
383 00000000010582f4: 0000: 70460004 0000001d 01011880 00000000 00000000
384 t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
385 { EVENT = PC_CCU_FLUSH_DEPTH_TS }
386 { ADDR_0_LO = 0x1011880 }
387 { ADDR_0_HI = 0 }
388 { 3 = 0 }
389 event PC_CCU_FLUSH_DEPTH_TS
390 0000000001058308: 0000: 70460004 0000001c 01011880 00000000 00000000
391 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
392 { EVENT = PC_CCU_INVALIDATE_COLOR }
393 event PC_CCU_INVALIDATE_COLOR
394 000000000105831c: 0000: 70460001 00000019
395 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
396 { EVENT = PC_CCU_INVALIDATE_DEPTH }
397 event PC_CCU_INVALIDATE_DEPTH
398 0000000001058324: 0000: 70460001 00000018
399 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
400 000000000105832c: 0000: 70268000
401 t4 write RB_CCU_CNTL (8e07)
402 RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM }
403 0000000001058330: 0000: 408e0701 7c400000
404 t4 write VPC_SO_DISABLE (9306)
405 VPC_SO_DISABLE: { 0 }
406 0000000001058338: 0000: 48930601 00000000
407 t4 write GRAS_BIN_CONTROL (80a1)
408 GRAS_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 }
409 0000000001058340: 0000: 4880a101 06001008
410 t4 write RB_BIN_CONTROL (8800)
411 RB_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 }
412 0000000001058348: 0000: 48880001 06001008
413 t4 write RB_BIN_CONTROL2 (88d3)
414 RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 }
415 0000000001058350: 0000: 4088d301 00001008
416 t7 opcode: CP_SET_MARKER (65) (2 dwords)
417 { MODE = RM6_YIELD | MARKER = RM6_YIELD }
418 0000000001058358: 0000: 70e50001 00000007
419 t7 opcode: CP_SET_MARKER (65) (2 dwords)
420 { MODE = RM6_GMEM | MARKER = RM6_GMEM }
421 0000000001058360: 0000: 70e50001 00000004
422 t4 write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
423 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
424 GRAS_SC_WINDOW_SCISSOR_BR: { X = 255 | Y = 255 }
425 0000000001058368: 0000: 4080f002 00000000 00ff00ff
426 t4 write GRAS_2D_RESOLVE_CNTL_1 (840a)
427 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 }
428 GRAS_2D_RESOLVE_CNTL_2: { X = 255 | Y = 255 }
429 0000000001058374: 0000: 48840a02 00000000 00ff00ff
430 t4 write RB_WINDOW_OFFSET (8890)
431 RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
432 0000000001058380: 0000: 48889001 00000000
433 t4 write RB_WINDOW_OFFSET2 (88d4)
434 RB_WINDOW_OFFSET2: { X = 0 | Y = 0 }
435 0000000001058388: 0000: 4888d401 00000000
436 t4 write SP_WINDOW_OFFSET (b4d1)
437 SP_WINDOW_OFFSET: { X = 0 | Y = 0 }
438 0000000001058390: 0000: 48b4d101 00000000
439 t4 write SP_TP_WINDOW_OFFSET (b307)
440 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
441 0000000001058398: 0000: 48b30701 00000000
442 t4 write VPC_SO_DISABLE (9306)
443 VPC_SO_DISABLE: { 0 }
444 00000000010583a0: 0000: 48930601 00000000
445 t7 opcode: CP_SET_VISIBILITY_OVERRIDE (64) (2 dwords)
446 00000000010583a8: 0000: 70640001 00000001
447 t7 opcode: CP_SET_MODE (63) (2 dwords)
448 00000000010583b0: 0000: 70e30001 00000000
449 t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
450 ibaddr:000000000115e000
451 ibsize:000000f1
452 t7 opcode: CP_COND_REG_EXEC (47) (3 dwords)
453 { REG0 = 0 | GMEM | MODE = RENDER_MODE }
454 { DWORDS = 23 }
455 000000000115e000: 0000: 70c70002 34000000 00000017
456 t4 write RB_BLIT_SCISSOR_TL (88d1)
457 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
458 RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
459 000000000115e00c: 0000: 4888d102 00000000 00ff00ff
460 t4 write RB_MSAA_CNTL (88d5)
461 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
462 000000000115e018: 0000: 4088d501 00000000
463 t4 write RB_BLIT_INFO (88e3)
464 RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 }
465 000000000115e020: 0000: 4088e301 00000003
466 t4 write RB_BLIT_DST_INFO (88d7)
467 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
468 RB_BLIT_DST: 0x1013000
469 RB_BLIT_DST+0x1: 0
470 RB_BLIT_DST_PITCH: 1024
471 000000000115e028: 0000: 4888d704 00001807 01013000 00000000 00000010
472 t4 write RB_BLIT_FLAG_DST (88dc)
473 RB_BLIT_FLAG_DST: 0x1012000
474 RB_BLIT_FLAG_DST+0x1: 0
475 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
476 000000000115e03c: 0000: 4088dc83 01012000 00000000 00004001
477 t4 write RB_BLIT_BASE_GMEM (88d6)
478 RB_BLIT_BASE_GMEM: 0
479 000000000115e04c: 0000: 4088d601 00000000
480 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
481 { EVENT = BLIT }
482 event BLIT
483 mode: RM6_GMEM
484 skip_ib2: g=0, l=0
485 draw[1] register values
486 !+ 06001008 GRAS_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 }
487 + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
488 !+ 00ff00ff GRAS_SC_WINDOW_SCISSOR_BR: { X = 255 | Y = 255 }
489 + 00000000 GRAS_2D_RESOLVE_CNTL_1: { X = 0 | Y = 0 }
490 !+ 00ff00ff GRAS_2D_RESOLVE_CNTL_2: { X = 255 | Y = 255 }
491 !+ 06001008 RB_BIN_CONTROL: { BINW = 256 | BINH = 256 | UNK22 = 0x18 }
492 + 00000000 RB_WINDOW_OFFSET: { X = 0 | Y = 0 }
493 + 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
494 !+ 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
495 !+ 00001008 RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 }
496 + 00000000 RB_WINDOW_OFFSET2: { X = 0 | Y = 0 }
497 + 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
498 + 00000000 RB_BLIT_BASE_GMEM: 0
499 !+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
500 !+ 01013000 RB_BLIT_DST: 0x1013000
501 + 00000000 RB_BLIT_DST+0x1: 0
502 !+ 00000010 RB_BLIT_DST_PITCH: 1024
503 !+ 01012000 RB_BLIT_FLAG_DST: 0x1012000
504 + 00000000 RB_BLIT_FLAG_DST+0x1: 0
505 !+ 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
506 !+ 00000003 RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 }
507 !+ 7c400000 RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM }
508 !+ 00000000 VPC_SO_DISABLE: { 0 }
509 + 00000000 SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
510 + 00000000 SP_WINDOW_OFFSET: { X = 0 | Y = 0 }
511 000000000115e054: 0000: 70460001 0000001e
512 t4 write RB_BLIT_SCISSOR_TL (88d1)
513 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
514 RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
515 000000000115e05c: 0000: 4888d102 00000000 00ff00ff
516 t7 opcode: CP_COND_REG_EXEC (47) (3 dwords)
517 { REG0 = 0 | SYSMEM | MODE = RENDER_MODE }
518 { DWORDS = 0 }
519 000000000115e068: 0000: 70c70002 38000000 00000000
520 t4 write RB_DEPTH_BUFFER_INFO (8872)
521 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
522 RB_DEPTH_BUFFER_PITCH: 0
523 RB_DEPTH_BUFFER_ARRAY_PITCH: 0
524 RB_DEPTH_BUFFER_BASE_LO: 0
525 RB_DEPTH_BUFFER_BASE_HI: 0
526 RB_DEPTH_BUFFER_BASE_GMEM: 0
527 000000000115e074: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000
528 t4 write GRAS_SU_DEPTH_BUFFER_INFO (8098)
529 GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
530 000000000115e090: 0000: 48809801 00000000
531 t4 write GRAS_LRZ_BUFFER_BASE_LO (8103)
532 GRAS_LRZ_BUFFER_BASE_LO: 0
533 GRAS_LRZ_BUFFER_BASE_HI: 0
534 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
535 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
536 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
537 000000000115e098: 0000: 48810385 00000000 00000000 00000000 00000000 00000000
538 t4 write RB_STENCIL_INFO (8881)
539 RB_STENCIL_INFO: { 0 }
540 000000000115e0b0: 0000: 48888101 00000000
541 t4 write RB_MRT[0].BUF_INFO (8822)
542 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX }
543 RB_MRT[0].PITCH: 1024
544 RB_MRT[0].ARRAY_PITCH: 262144
545 RB_MRT[0].BASE_LO: 0x1013000
546 RB_MRT[0].BASE_HI: 0
547 RB_MRT[0].BASE_GMEM: 0
548 000000000115e0b8: 0000: 48882286 00000330 00000010 00001000 01013000 00000000 00000000
549 t4 write SP_FS_MRT[0].REG (a996)
550 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
551 000000000115e0d4: 0000: 48a99601 00000030
552 t4 write RB_MRT_FLAG_BUFFER[0].ADDR_LO (8903)
553 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0x1012000
554 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
555 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
556 000000000115e0dc: 0000: 40890383 01012000 00000000 00004001
557 t4 write RB_SRGB_CNTL (880f)
558 RB_SRGB_CNTL: { 0 }
559 000000000115e0ec: 0000: 48880f01 00000000
560 t4 write SP_SRGB_CNTL (a98a)
561 SP_SRGB_CNTL: { 0 }
562 000000000115e0f4: 0000: 40a98a01 00000000
563 t4 write GRAS_MAX_LAYER_INDEX (8004)
564 GRAS_MAX_LAYER_INDEX: 0
565 000000000115e0fc: 0000: 48800401 00000000
566 t4 write SP_TP_RAS_MSAA_CNTL (b300)
567 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
568 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
569 000000000115e104: 0000: 40b30002 00000000 00000004
570 t4 write GRAS_RAS_MSAA_CNTL (80a2)
571 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
572 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
573 000000000115e110: 0000: 4880a202 00000000 00000004
574 t4 write RB_RAS_MSAA_CNTL (8802)
575 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
576 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
577 000000000115e11c: 0000: 40880202 00000000 00000004
578 t4 write RB_MSAA_CNTL (88d5)
579 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
580 000000000115e128: 0000: 4088d501 00000000
581 t7 opcode: CP_COND_REG_EXEC (47) (3 dwords)
582 { REG0 = 0 | GMEM | SYSMEM | MODE = RENDER_MODE }
583 { DWORDS = 4 }
584 000000000115e130: 0000: 70c70002 3c000000 00000004
585 t7 opcode: CP_REG_WRITE (6d) (4 dwords)
586 { TRACKER = TRACK_RENDER_CNTL }
587 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0x1 }
588 000000000115e13c: 0000: 706d8003 00000002 00008801 00010010
589 t7 opcode: CP_SET_DRAW_STATE (43) (7 dwords)
590 { COUNT = 0 | DISABLE | GMEM | GROUP_ID = 17 }
591 { ADDR_LO = 0 }
592 { ADDR_HI = 0 }
593 { COUNT = 0 | DISABLE | SYSMEM | GROUP_ID = 18 }
594 { ADDR_LO = 0 }
595 { ADDR_HI = 0 }
596 000000000115e14c: 0000: 70438006 11220000 00000000 00000000 12420000 00000000 00000000
597 t7 opcode: CP_SET_DRAW_STATE (43) (52 dwords)
598 { COUNT = 157 | GMEM | SYSMEM | GROUP_ID = 0 }
599 { ADDR_LO = 0x1054180 }
600 { ADDR_HI = 0 }
601 { COUNT = 139 | BINNING | GROUP_ID = 1 }
602 { ADDR_LO = 0x10543f4 }
603 { ADDR_HI = 0 }
604 { COUNT = 19 | GMEM | SYSMEM | GROUP_ID = 4 }
605 { ADDR_LO = 0x1054620 }
606 { ADDR_HI = 0 }
607 { COUNT = 19 | BINNING | GROUP_ID = 5 }
608 { ADDR_LO = 0x105466c }
609 { ADDR_HI = 0 }
610 { COUNT = 9 | BINNING | GMEM | SYSMEM | GROUP_ID = 6 }
611 { ADDR_LO = 0x105470c }
612 { ADDR_HI = 0 }
613 { COUNT = 6 | BINNING | GMEM | SYSMEM | GROUP_ID = 7 }
614 { ADDR_LO = 0x1054748 }
615 { ADDR_HI = 0 }
616 { COUNT = 7 | BINNING | GMEM | SYSMEM | GROUP_ID = 8 }
617 { ADDR_LO = 0x1054784 }
618 { ADDR_HI = 0 }
619 { COUNT = 18 | BINNING | GMEM | SYSMEM | GROUP_ID = 19 }
620 { ADDR_LO = 0x10546b8 }
621 { ADDR_HI = 0 }
622 { COUNT = 3 | BINNING | GMEM | SYSMEM | GROUP_ID = 20 }
623 { ADDR_LO = 0x1054700 }
624 { ADDR_HI = 0 }
625 { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 21 }
626 { ADDR_LO = 0x1054730 }
627 { ADDR_HI = 0 }
628 { COUNT = 4 | BINNING | GMEM | SYSMEM | GROUP_ID = 22 }
629 { ADDR_LO = 0x1054738 }
630 { ADDR_HI = 0 }
631 { COUNT = 5 | BINNING | GMEM | SYSMEM | GROUP_ID = 23 }
632 { ADDR_LO = 0x10547a0 }
633 { ADDR_HI = 0 }
634 { COUNT = 3 | BINNING | GMEM | SYSMEM | GROUP_ID = 24 }
635 { ADDR_LO = 0x1054760 }
636 { ADDR_HI = 0 }
637 { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 25 }
638 { ADDR_LO = 0x105476c }
639 { ADDR_HI = 0 }
640 { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 26 }
641 { ADDR_LO = 0x1054774 }
642 { ADDR_HI = 0 }
643 { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 27 }
644 { ADDR_LO = 0x105477c }
645 { ADDR_HI = 0 }
646 { COUNT = 6 | BINNING | GMEM | SYSMEM | GROUP_ID = 28 }
647 { ADDR_LO = 0x10547b4 }
648 { ADDR_HI = 0 }
649 000000000115e168: 0000: 70438033 0060009d 01054180 00000000 0110008b 010543f4 00000000 04600013
650 000000000115e188: 0020: 01054620 00000000 05100013 0105466c 00000000 06700009 0105470c 00000000
651 000000000115e1a8: 0040: 07700006 01054748 00000000 08700007 01054784 00000000 13700012 010546b8
652 000000000115e1c8: 0060: 00000000 14700003 01054700 00000000 15700002 01054730 00000000 16700004
653 000000000115e1e8: 0080: 01054738 00000000 17700005 010547a0 00000000 18700003 01054760 00000000
654 000000000115e208: 00a0: 19700002 0105476c 00000000 1a700002 01054774 00000000 1b700002 0105477c
655 000000000115e228: 00c0: 00000000 1c700006 010547b4 00000000
656 t4 write PC_RESTART_INDEX (9803)
657 PC_RESTART_INDEX: 4294967295
658 000000000115e238: 0000: 40980301 ffffffff
659 t7 opcode: CP_WAIT_FOR_ME (13) (1 dwords)
660 000000000115e240: 0000: 70138000
661 t4 write PC_PRIMITIVE_CNTL_0 (9b00)
662 PC_PRIMITIVE_CNTL_0: { 0 }
663 000000000115e244: 0000: 409b0001 00000000
664 t7 opcode: CP_SET_DRAW_STATE (43) (82 dwords)
665 { COUNT = 157 | GMEM | SYSMEM | GROUP_ID = 0 }
666 { ADDR_LO = 0x1054180 }
667 { ADDR_HI = 0 }
668 { COUNT = 139 | BINNING | GROUP_ID = 1 }
669 { ADDR_LO = 0x10543f4 }
670 { ADDR_HI = 0 }
671 { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 2 }
672 { ADDR_LO = 0 }
673 { ADDR_HI = 0 }
674 { COUNT = 19 | GMEM | SYSMEM | GROUP_ID = 4 }
675 { ADDR_LO = 0x1054620 }
676 { ADDR_HI = 0 }
677 { COUNT = 19 | BINNING | GROUP_ID = 5 }
678 { ADDR_LO = 0x105466c }
679 { ADDR_HI = 0 }
680 { COUNT = 9 | BINNING | GMEM | SYSMEM | GROUP_ID = 6 }
681 { ADDR_LO = 0x105470c }
682 { ADDR_HI = 0 }
683 { COUNT = 6 | BINNING | GMEM | SYSMEM | GROUP_ID = 7 }
684 { ADDR_LO = 0x1054748 }
685 { ADDR_HI = 0 }
686 { COUNT = 7 | BINNING | GMEM | SYSMEM | GROUP_ID = 8 }
687 { ADDR_LO = 0x1054784 }
688 { ADDR_HI = 0 }
689 { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 9 }
690 { ADDR_LO = 0x115c070 }
691 { ADDR_HI = 0 }
692 { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 10 }
693 { ADDR_LO = 0x115c070 }
694 { ADDR_HI = 0 }
695 { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 11 }
696 { ADDR_LO = 0x115c070 }
697 { ADDR_HI = 0 }
698 { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 12 }
699 { ADDR_LO = 0x115c070 }
700 { ADDR_HI = 0 }
701 { COUNT = 0 | DISABLE | GMEM | SYSMEM | GROUP_ID = 13 }
702 { ADDR_LO = 0x115c070 }
703 { ADDR_HI = 0 }
704 { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 14 }
705 { ADDR_LO = 0 }
706 { ADDR_HI = 0 }
707 { COUNT = 0 | DIRTY | DISABLE | GMEM | SYSMEM | GROUP_ID = 15 }
708 { ADDR_LO = 0 }
709 { ADDR_HI = 0 }
710 { COUNT = 4 | BINNING | GMEM | SYSMEM | GROUP_ID = 3 }
711 { ADDR_LO = 0x115c070 }
712 { ADDR_HI = 0 }
713 { COUNT = 0 | DISABLE | BINNING | GMEM | SYSMEM | GROUP_ID = 16 }
714 { ADDR_LO = 0 }
715 { ADDR_HI = 0 }
716 { COUNT = 18 | BINNING | GMEM | SYSMEM | GROUP_ID = 19 }
717 { ADDR_LO = 0x10546b8 }
718 { ADDR_HI = 0 }
719 { COUNT = 3 | BINNING | GMEM | SYSMEM | GROUP_ID = 20 }
720 { ADDR_LO = 0x1054700 }
721 { ADDR_HI = 0 }
722 { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 21 }
723 { ADDR_LO = 0x1054730 }
724 { ADDR_HI = 0 }
725 { COUNT = 4 | BINNING | GMEM | SYSMEM | GROUP_ID = 22 }
726 { ADDR_LO = 0x1054738 }
727 { ADDR_HI = 0 }
728 { COUNT = 5 | BINNING | GMEM | SYSMEM | GROUP_ID = 23 }
729 { ADDR_LO = 0x10547a0 }
730 { ADDR_HI = 0 }
731 { COUNT = 3 | BINNING | GMEM | SYSMEM | GROUP_ID = 24 }
732 { ADDR_LO = 0x1054760 }
733 { ADDR_HI = 0 }
734 { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 25 }
735 { ADDR_LO = 0x105476c }
736 { ADDR_HI = 0 }
737 { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 26 }
738 { ADDR_LO = 0x1054774 }
739 { ADDR_HI = 0 }
740 { COUNT = 2 | BINNING | GMEM | SYSMEM | GROUP_ID = 27 }
741 { ADDR_LO = 0x105477c }
742 { ADDR_HI = 0 }
743 { COUNT = 6 | BINNING | GMEM | SYSMEM | GROUP_ID = 28 }
744 { ADDR_LO = 0x10547b4 }
745 { ADDR_HI = 0 }
746 000000000115e24c: 0000: 70430051 0060009d 01054180 00000000 0110008b 010543f4 00000000 02720000
747 000000000115e26c: 0020: 00000000 00000000 04600013 01054620 00000000 05100013 0105466c 00000000
748 000000000115e28c: 0040: 06700009 0105470c 00000000 07700006 01054748 00000000 08700007 01054784
749 000000000115e2ac: 0060: 00000000 09720000 0115c070 00000000 0a720000 0115c070 00000000 0b720000
750 000000000115e2cc: 0080: 0115c070 00000000 0c720000 0115c070 00000000 0d620000 0115c070 00000000
751 000000000115e2ec: 00a0: 0e720000 00000000 00000000 0f630000 00000000 00000000 03700004 0115c070
752 000000000115e30c: 00c0: 00000000 10720000 00000000 00000000 13700012 010546b8 00000000 14700003
753 000000000115e32c: 00e0: 01054700 00000000 15700002 01054730 00000000 16700004 01054738 00000000
754 000000000115e34c: 0100: 17700005 010547a0 00000000 18700003 01054760 00000000 19700002 0105476c
755 000000000115e36c: 0120: 00000000 1a700002 01054774 00000000 1b700002 0105477c 00000000 1c700006
756 000000000115e38c: 0140: 010547b4 00000000
757 group_id: 0
758 count: 157
759 addr: 0000000001054180
760 flags: 0
761 enable_mask: 0x6
762 0000000001054180: 0000: 40bb0801 0000009f 40a80001 80100180 48a82302 00000100 00000001 48b80001
763 00000000010541a0: 0020: 00000101 48a81c02 01054000 00000000 70328003 00620000 01054000 00000000
764 00000000010541c0: 0040: 70320007 00604001 00000000 00000000 3f800000 00000000 d0d0d0d0 d0d0d0d0
765 00000000010541e0: 0060: 48a83b01 00000000 40b80101 00000000 40a86301 00000000 40b80201 00000000
766 0000000001054200: 0080: 48a89401 00000000 48b80301 00000000 40a98001 81500100 48ab0402 00000100
767 0000000001054220: 00a0: 00000001 40bb1001 00000100 40a98302 01054080 00000000 70348003 00720000
768 0000000001054240: 00c0: 01054080 00000000 48a9bb01 00000000 40b98701 00000000 48a83101 00000000
769 0000000001054260: 00e0: 40a00186 fcfcfc09 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000 40921204
770 0000000001054280: 0100: fffffff0 ffffffff ffffffff ffffffff 70dc0004 00009216 00000000 00009305
771 00000000010542a0: 0120: 00000000 40a80301 0f000f08 48a81301 00000400 40930101 00ff0408 48910101
772 00000000010542c0: 0140: 00ffff00 48800101 00000000 489b0101 00000008 48a80201 00000002 48910401
773 00000000010542e0: 0160: 0000ffff 48809b01 00000000 40980601 00000000 40930401 ff01ff04 40920008
774 *
775 0000000001054320: 01a0: 48920808 00000000 00000000 00000000 00000000 00000000 00000000 00000000
776 0000000001054340: 01c0: 00000000 40a99e01 00007fc0 40b98285 00000007 fcfcfcfc fcfcfc00 fcfcfcfc
777 0000000001054360: 01e0: 000000fc 48b98001 00000003 40800501 00000001 48880902 00000401 00000000
778 0000000001054380: 0200: 40881001 00000000 40810101 00000000 48810901 00000000 40a98c02 fcfcfc00
779 00000000010543a0: 0220: 00000001 48a98e08 00000002 000000fc 000000fc 000000fc 000000fc 000000fc
780 00000000010543c0: 0240: 000000fc 000000fc 48a98b01 0000000f 40880b02 00000000 00000001 40880d01
781 00000000010543e0: 0260: 0000000f 48809401 00000000 40887001 00000000
782 t4 write HLSQ_INVALIDATE_CMD (bb08)
783 HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
784 0000000001054180: 0000: 40bb0801 0000009f
785 t4 write SP_VS_CTRL_REG0 (a800)
786 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | MERGEDREGS }
787 0000000001054188: 0000: 40a80001 80100180
788 t4 write SP_VS_CONFIG (a823)
789 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
790 SP_VS_INSTRLEN: 1
791 0000000001054190: 0000: 48a82302 00000100 00000001
792 t4 write HLSQ_VS_CNTL (b800)
793 HLSQ_VS_CNTL: { CONSTLEN = 4 | ENABLED }
794 000000000105419c: 0000: 48b80001 00000101
795 t4 write SP_VS_OBJ_START_LO (a81c)
796 SP_VS_OBJ_START_LO: 0x1054000 base=1054000, offset=0, size=12288
797 SP_VS_OBJ_START_HI: 0 base=1054000, offset=0, size=12288
798 0000000001054000: 0000: 00080009 42bc080b 10040004 64858008 10050005 64858009 10050006 6485800a
799 0000000001054020: 0020: 10040007 6485800b 00000000 03000000 00000000 00000000 00000000 00000000
800 *
801 0000000001054080: 0080: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005
802 00000000010540a0: 00a0: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
803 *
804 :2:0000:0000[42bc080bx_00080009x] (nop3) cmps.s.eq r2.w, r2.y, r2.x
805 :3:0001:0004[64858008x_10040004x] sel.b32 r2.x, r1.x, r2.w, c1.x
806 :3:0002:0005[64858009x_10050005x] sel.b32 r2.y, r1.y, r2.w, c1.y
807 :3:0003:0006[6485800ax_10050006x] sel.b32 r2.z, r1.z, r2.w, c1.y
808 :3:0004:0007[6485800bx_10040007x] sel.b32 r2.w, r1.w, r2.w, c1.x
809 :0:0005:0008[03000000x_00000000x] end
810 :0:0006:0009[00000000x_00000000x] nop
811 :0:0007:0010[00000000x_00000000x] nop
812 :0:0008:0011[00000000x_00000000x] nop
813 :0:0009:0012[00000000x_00000000x] nop
814 Register Stats:
815 - used (half): 8-23 (cnt=16, max=23)
816 - used (full): 4-11 (cnt=8, max=11)
817 - input (half): 8-19 (cnt=12, max=19)
818 - input (full): 4-9 (cnt=6, max=9)
819 - max const: 5
820
821 - output (half): 16-23 (cnt=8, max=23) (estimated)
822 - output (full): 8-11 (cnt=4, max=11) (estimated)
823 - shaderdb: 13 instructions, 7 nops, 6 non-nops, (10 instlen), 0 last-baryf, 0 half, 3 full
824 - shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
825 - shaderdb: 0 (ss), 0 (sy)
826 00000000010541a4: 0000: 48a81c02 01054000 00000000
827 t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
828 { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
829 { EXT_SRC_ADDR = 0x1054000 }
830 { EXT_SRC_ADDR_HI = 0 }
831 :2:0000:0000[42bc080bx_00080009x] (nop3) cmps.s.eq r2.w, r2.y, r2.x
832 :3:0001:0004[64858008x_10040004x] sel.b32 r2.x, r1.x, r2.w, c1.x
833 :3:0002:0005[64858009x_10050005x] sel.b32 r2.y, r1.y, r2.w, c1.y
834 :3:0003:0006[6485800ax_10050006x] sel.b32 r2.z, r1.z, r2.w, c1.y
835 :3:0004:0007[6485800bx_10040007x] sel.b32 r2.w, r1.w, r2.w, c1.x
836 :0:0005:0008[03000000x_00000000x] end
837 :0:0006:0009[00000000x_00000000x] nop
838 :0:0007:0010[00000000x_00000000x] nop
839 :0:0008:0011[00000000x_00000000x] nop
840 :0:0009:0012[00000000x_00000000x] nop
841 Register Stats:
842 - used (half): 8-23 (cnt=16, max=23)
843 - used (full): 4-11 (cnt=8, max=11)
844 - input (half): 8-19 (cnt=12, max=19)
845 - input (full): 4-9 (cnt=6, max=9)
846 - max const: 5
847
848 - output (half): 16-23 (cnt=8, max=23) (estimated)
849 - output (full): 8-11 (cnt=4, max=11) (estimated)
850 - shaderdb: 13 instructions, 7 nops, 6 non-nops, (10 instlen), 0 last-baryf, 0 half, 3 full
851 - shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
852 - shaderdb: 0 (ss), 0 (sy)
853 00000000010541b0: 0000: 70328003 00620000 01054000 00000000
854 t7 opcode: CP_LOAD_STATE6_GEOM (32) (8 dwords)
855 { DST_OFF = 1 | STATE_TYPE = ST6_CONSTANTS | STATE_SRC = SS6_DIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
856 { EXT_SRC_ADDR = 0 }
857 { EXT_SRC_ADDR_HI = 0 }
858 00000000010541d0: 1.000000 0.000000 -28026765312.000000 -28026765312.000000
859 00000000010541d0: 0000: 3f800000 00000000 d0d0d0d0 d0d0d0d0
860 00000000010541c0: 0000: 70320007 00604001 00000000 00000000 3f800000 00000000 d0d0d0d0 d0d0d0d0
861 t4 write SP_HS_CONFIG (a83b)
862 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
863 00000000010541e0: 0000: 48a83b01 00000000
864 t4 write HLSQ_HS_CNTL (b801)
865 HLSQ_HS_CNTL: { CONSTLEN = 0 }
866 00000000010541e8: 0000: 40b80101 00000000
867 t4 write SP_DS_CONFIG (a863)
868 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
869 00000000010541f0: 0000: 40a86301 00000000
870 t4 write HLSQ_DS_CNTL (b802)
871 HLSQ_DS_CNTL: { CONSTLEN = 0 }
872 00000000010541f8: 0000: 40b80201 00000000
873 t4 write SP_GS_CONFIG (a894)
874 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
875 0000000001054200: 0000: 48a89401 00000000
876 t4 write HLSQ_GS_CNTL (b803)
877 HLSQ_GS_CNTL: { CONSTLEN = 0 }
878 0000000001054208: 0000: 48b80301 00000000
879 t4 write SP_FS_CTRL_REG0 (a980)
880 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | VARYING | MERGEDREGS | 0x1000000 }
881 0000000001054210: 0000: 40a98001 81500100
882 t4 write SP_FS_CONFIG (ab04)
883 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
884 SP_FS_INSTRLEN: 1
885 0000000001054218: 0000: 48ab0402 00000100 00000001
886 t4 write HLSQ_FS_CNTL (bb10)
887 HLSQ_FS_CNTL: { CONSTLEN = 0 | ENABLED }
888 0000000001054224: 0000: 40bb1001 00000100
889 t4 write SP_FS_OBJ_START_LO (a983)
890 SP_FS_OBJ_START_LO: 0x1054080 base=1054000, offset=128, size=12288
891 SP_FS_OBJ_START_HI: 0 base=1054000, offset=128, size=12288
892 0000000001054080: 0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005
893 00000000010540a0: 0020: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
894 *
895 0000000001054100: 0080: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
896 *
897 :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x
898 :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x
899 :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x
900 :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x
901 :0:0004:0004[03000000x_00000000x] end
902 :0:0005:0005[00000000x_00000000x] nop
903 :0:0006:0006[00000000x_00000000x] nop
904 :0:0007:0007[00000000x_00000000x] nop
905 :0:0008:0008[00000000x_00000000x] nop
906 Register Stats:
907 - used (half): 0-1 4-11 (cnt=10, max=11)
908 - used (full): 0 2-5 (cnt=5, max=5)
909 - input (half): 0-1 (cnt=2, max=1)
910 - input (full): 0 (cnt=1, max=0)
911 - max const: 0
912
913 - output (half): 4-11 (cnt=8, max=11) (estimated)
914 - output (full): 2-5 (cnt=4, max=5) (estimated)
915 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 3 last-baryf, 0 half, 2 full
916 - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
917 - shaderdb: 0 (ss), 0 (sy)
918 000000000105422c: 0000: 40a98302 01054080 00000000
919 t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
920 { DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 1 }
921 { EXT_SRC_ADDR = 0x1054080 }
922 { EXT_SRC_ADDR_HI = 0 }
923 :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x
924 :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x
925 :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x
926 :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x
927 :0:0004:0004[03000000x_00000000x] end
928 :0:0005:0005[00000000x_00000000x] nop
929 :0:0006:0006[00000000x_00000000x] nop
930 :0:0007:0007[00000000x_00000000x] nop
931 :0:0008:0008[00000000x_00000000x] nop
932 Register Stats:
933 - used (half): 0-1 4-11 (cnt=10, max=11)
934 - used (full): 0 2-5 (cnt=5, max=5)
935 - input (half): 0-1 (cnt=2, max=1)
936 - input (full): 0 (cnt=1, max=0)
937 - max const: 0
938
939 - output (half): 4-11 (cnt=8, max=11) (estimated)
940 - output (full): 2-5 (cnt=4, max=5) (estimated)
941 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 3 last-baryf, 0 half, 2 full
942 - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
943 - shaderdb: 0 (ss), 0 (sy)
944 0000000001054238: 0000: 70348003 00720000 01054080 00000000
945 t4 write SP_CS_CONFIG (a9bb)
946 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
947 0000000001054248: 0000: 48a9bb01 00000000
948 t4 write HLSQ_CS_CNTL (b987)
949 HLSQ_CS_CNTL: { CONSTLEN = 0 }
950 0000000001054250: 0000: 40b98701 00000000
951 t4 write SP_HS_UNKNOWN_A831 (a831)
952 SP_HS_UNKNOWN_A831: 0
953 0000000001054258: 0000: 48a83101 00000000
954 t4 write VFD_CONTROL_1 (a001)
955 VFD_CONTROL_1: { REGID4VTX = r2.y | REGID4INST = r63.x | REGID4PRIMID = r63.x | 0xfc000000 }
956 VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
957 VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc }
958 VFD_CONTROL_4: 0xfc
959 VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 }
960 VFD_CONTROL_6: { 0 }
961 0000000001054260: 0000: 40a00186 fcfcfc09 0000fcfc fcfcfcfc 000000fc 0000fcfc 00000000
962 t4 write VPC_VAR[0].DISABLE (9212)
963 VPC_VAR[0].DISABLE: 0xfffffff0
964 VPC_VAR[0x1].DISABLE: 0xffffffff
965 VPC_VAR[0x2].DISABLE: 0xffffffff
966 VPC_VAR[0x3].DISABLE: 0xffffffff
967 000000000105427c: 0000: 40921204 fffffff0 ffffffff ffffffff ffffffff
968 t7 opcode: CP_CONTEXT_REG_BUNCH (5c) (5 dwords)
969 VPC_SO_CNTL: { 0 }
970 VPC_SO_BUF_CNTL: { 0 }
971 0000000001054290: 0000: 70dc0004 00009216 00000000 00009305 00000000
972 t4 write SP_VS_OUT[0].REG (a803)
973 SP_VS_OUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf }
974 00000000010542a4: 0000: 40a80301 0f000f08
975 t4 write SP_VS_VPC_DST[0].REG (a813)
976 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 0 | OUTLOC3 = 0 }
977 00000000010542ac: 0000: 48a81301 00000400
978 t4 write VPC_VS_PACK (9301)
979 VPC_VS_PACK: { STRIDE_IN_VPC = 8 | POSITIONLOC = 4 | PSIZELOC = 255 }
980 00000000010542b4: 0000: 40930101 00ff0408
981 t4 write VPC_VS_CLIP_CNTL (9101)
982 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
983 00000000010542bc: 0000: 48910101 00ffff00
984 t4 write GRAS_VS_CL_CNTL (8001)
985 GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 }
986 00000000010542c4: 0000: 48800101 00000000
987 t4 write PC_VS_OUT_CNTL (9b01)
988 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 8 | CLIP_MASK = 0 }
989 00000000010542cc: 0000: 489b0101 00000008
990 t4 write SP_VS_PRIMITIVE_CNTL (a802)
991 SP_VS_PRIMITIVE_CNTL: { OUT = 2 }
992 00000000010542d4: 0000: 48a80201 00000002
993 t4 write VPC_VS_LAYER_CNTL (9104)
994 VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
995 00000000010542dc: 0000: 48910401 0000ffff
996 t4 write GRAS_VS_LAYER_CNTL (809b)
997 GRAS_VS_LAYER_CNTL: { 0 }
998 00000000010542e4: 0000: 48809b01 00000000
999 t4 write PC_PRIMID_PASSTHRU (9806)
1000 PC_PRIMID_PASSTHRU: FALSE
1001 00000000010542ec: 0000: 40980601 00000000
1002 t4 write VPC_CNTL_0 (9304)
1003 VPC_CNTL_0: { NUMNONPOSVAR = 4 | PRIMIDLOC = 255 | VARYING | UNKLOC = 255 }
1004 00000000010542f4: 0000: 40930401 ff01ff04
1005 t4 write VPC_VARYING_INTERP[0].MODE (9200)
1006 VPC_VARYING_INTERP[0].MODE: 0
1007 VPC_VARYING_INTERP[0x1].MODE: 0
1008 VPC_VARYING_INTERP[0x2].MODE: 0
1009 VPC_VARYING_INTERP[0x3].MODE: 0
1010 VPC_VARYING_INTERP[0x4].MODE: 0
1011 VPC_VARYING_INTERP[0x5].MODE: 0
1012 VPC_VARYING_INTERP[0x6].MODE: 0
1013 VPC_VARYING_INTERP[0x7].MODE: 0
1014 00000000010542fc: 0000: 40920008 00000000 00000000 00000000 00000000 00000000 00000000 00000000
1015 *
1016 t4 write VPC_VARYING_PS_REPL[0].MODE (9208)
1017 VPC_VARYING_PS_REPL[0].MODE: 0
1018 VPC_VARYING_PS_REPL[0x1].MODE: 0
1019 VPC_VARYING_PS_REPL[0x2].MODE: 0
1020 VPC_VARYING_PS_REPL[0x3].MODE: 0
1021 VPC_VARYING_PS_REPL[0x4].MODE: 0
1022 VPC_VARYING_PS_REPL[0x5].MODE: 0
1023 VPC_VARYING_PS_REPL[0x6].MODE: 0
1024 VPC_VARYING_PS_REPL[0x7].MODE: 0
1025 0000000001054320: 0000: 48920808 00000000 00000000 00000000 00000000 00000000 00000000 00000000
1026 *
1027 t4 write SP_FS_PREFETCH_CNTL (a99e)
1028 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 }
1029 0000000001054344: 0000: 40a99e01 00007fc0
1030 t4 write HLSQ_CONTROL_1_REG (b982)
1031 HLSQ_CONTROL_1_REG: 0x7
1032 HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x }
1033 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
1034 HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
1035 HLSQ_CONTROL_5_REG: 0xfc
1036 000000000105434c: 0000: 40b98285 00000007 fcfcfcfc fcfcfc00 fcfcfcfc 000000fc
1037 t4 write HLSQ_UNKNOWN_B980 (b980)
1038 HLSQ_UNKNOWN_B980: 0x3
1039 0000000001054364: 0000: 48b98001 00000003
1040 t4 write GRAS_CNTL (8005)
1041 GRAS_CNTL: { IJ_PERSP_PIXEL | COORD_MASK = 0 }
1042 000000000105436c: 0000: 40800501 00000001
1043 t4 write RB_RENDER_CONTROL0 (8809)
1044 RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 }
1045 RB_RENDER_CONTROL1: { 0 }
1046 0000000001054374: 0000: 48880902 00000401 00000000
1047 t4 write RB_SAMPLE_CNTL (8810)
1048 RB_SAMPLE_CNTL: { 0 }
1049 0000000001054380: 0000: 40881001 00000000
1050 t4 write GRAS_UNKNOWN_8101 (8101)
1051 GRAS_UNKNOWN_8101: 0
1052 0000000001054388: 0000: 40810101 00000000
1053 t4 write GRAS_SAMPLE_CNTL (8109)
1054 GRAS_SAMPLE_CNTL: { 0 }
1055 0000000001054390: 0000: 48810901 00000000
1056 t4 write SP_FS_OUTPUT_CNTL0 (a98c)
1057 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
1058 SP_FS_OUTPUT_CNTL1: { MRT = 1 }
1059 0000000001054398: 0000: 40a98c02 fcfcfc00 00000001
1060 t4 write SP_FS_OUTPUT[0].REG (a98e)
1061 SP_FS_OUTPUT[0].REG: { REGID = r0.z }
1062 SP_FS_OUTPUT[0x1].REG: { REGID = r63.x }
1063 SP_FS_OUTPUT[0x2].REG: { REGID = r63.x }
1064 SP_FS_OUTPUT[0x3].REG: { REGID = r63.x }
1065 SP_FS_OUTPUT[0x4].REG: { REGID = r63.x }
1066 SP_FS_OUTPUT[0x5].REG: { REGID = r63.x }
1067 SP_FS_OUTPUT[0x6].REG: { REGID = r63.x }
1068 SP_FS_OUTPUT[0x7].REG: { REGID = r63.x }
1069 00000000010543a4: 0000: 48a98e08 00000002 000000fc 000000fc 000000fc 000000fc 000000fc 000000fc
1070 00000000010543c4: 0020: 000000fc
1071 t4 write SP_FS_RENDER_COMPONENTS (a98b)
1072 SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
1073 00000000010543c8: 0000: 48a98b01 0000000f
1074 t4 write RB_FS_OUTPUT_CNTL0 (880b)
1075 RB_FS_OUTPUT_CNTL0: { 0 }
1076 RB_FS_OUTPUT_CNTL1: { MRT = 1 }
1077 00000000010543d0: 0000: 40880b02 00000000 00000001
1078 t4 write RB_RENDER_COMPONENTS (880d)
1079 RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
1080 00000000010543dc: 0000: 40880d01 0000000f
1081 t4 write GRAS_SU_DEPTH_PLANE_CNTL (8094)
1082 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
1083 00000000010543e4: 0000: 48809401 00000000
1084 t4 write RB_DEPTH_PLANE_CNTL (8870)
1085 RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
1086 00000000010543ec: 0000: 40887001 00000000
1087 group_id: 1
1088 count: 139
1089 addr: 00000000010543f4
1090 flags: 0
1091 enable_mask: 0x1
1092 skipped!
1093
1094 group_id: 3
1095 count: 4
1096 addr: 000000000115c070
1097 flags: 0
1098 enable_mask: 0x7
1099 000000000115c070: 0000: 40a01083 01053000 00000000 00000318
1100 t4 write VFD_FETCH[0].BASE (a010)
1101 VFD_FETCH[0].BASE: 0x1053000
1102 VFD_FETCH[0].BASE+0x1: 0
1103 VFD_FETCH[0].SIZE: 792
1104 000000000115c070: 0000: 40a01083 01053000 00000000 00000318
1105 group_id: 4
1106 count: 19
1107 addr: 0000000001054620
1108 flags: 0
1109 enable_mask: 0x6
1110 0000000001054620: 0000: 40a01301 00000024 48a09002 c8200000 00000001 40a0d001 0000000f 40a09202
1111 0000000001054640: 0020: c8200200 00000001 48a0d101 0000004f 40a09402 44c00400 00000001 48a0d201
1112 0000000001054660: 0040: 00000081 48a00001 00000303
1113 t4 write VFD_FETCH[0].STRIDE (a013)
1114 VFD_FETCH[0].STRIDE: 36
1115 0000000001054620: 0000: 40a01301 00000024
1116 t4 write VFD_DECODE[0].INSTR (a090)
1117 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
1118 VFD_DECODE[0].STEP_RATE: 0x1
1119 0000000001054628: 0000: 48a09002 c8200000 00000001
1120 t4 write VFD_DEST_CNTL[0].INSTR (a0d0)
1121 VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x }
1122 0000000001054634: 0000: 40a0d001 0000000f
1123 t4 write VFD_DECODE[0x1].INSTR (a092)
1124 VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
1125 VFD_DECODE[0x1].STEP_RATE: 0x1
1126 000000000105463c: 0000: 40a09202 c8200200 00000001
1127 t4 write VFD_DEST_CNTL[0x1].INSTR (a0d1)
1128 VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0xf | REGID = r1.x }
1129 0000000001054648: 0000: 48a0d101 0000004f
1130 t4 write VFD_DECODE[0x2].INSTR (a094)
1131 VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x20 | FORMAT = FMT6_32_SINT | SWAP = WZYX | UNK30 }
1132 VFD_DECODE[0x2].STEP_RATE: 0x1
1133 0000000001054650: 0000: 40a09402 44c00400 00000001
1134 t4 write VFD_DEST_CNTL[0x2].INSTR (a0d2)
1135 VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x1 | REGID = r2.x }
1136 000000000105465c: 0000: 48a0d201 00000081
1137 t4 write VFD_CONTROL_0 (a000)
1138 VFD_CONTROL_0: { FETCH_CNT = 3 | DECODE_CNT = 3 }
1139 0000000001054664: 0000: 48a00001 00000303
1140 group_id: 5
1141 count: 19
1142 addr: 000000000105466c
1143 flags: 0
1144 enable_mask: 0x1
1145 skipped!
1146
1147 group_id: 6
1148 count: 9
1149 addr: 000000000105470c
1150 flags: 0
1151 enable_mask: 0x7
1152 000000000105470c: 0000: 40800001 000000c0 48910801 00000003 48998101 00000003 48809102 ffc00001
1153 000000000105472c: 0020: 00000010
1154 t4 write GRAS_CL_CNTL (8000)
1155 GRAS_CL_CNTL: { ZERO_GB_SCALE_Z | VP_CLIP_CODE_IGNORE }
1156 000000000105470c: 0000: 40800001 000000c0
1157 t4 write VPC_POLYGON_MODE (9108)
1158 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
1159 0000000001054714: 0000: 48910801 00000003
1160 t4 write PC_POLYGON_MODE (9981)
1161 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
1162 000000000105471c: 0000: 48998101 00000003
1163 t4 write GRAS_SU_POINT_MINMAX (8091)
1164 GRAS_SU_POINT_MINMAX: { MIN = 0.062500 | MAX = 4092.000000 }
1165 GRAS_SU_POINT_SIZE: 1.000000
1166 0000000001054724: 0000: 48809102 ffc00001 00000010
1167 group_id: 7
1168 count: 6
1169 addr: 0000000001054748
1170 flags: 0
1171 enable_mask: 0x7
1172 0000000001054748: 0000: 40886401 00000000 48887101 00000000 40888001 00000000
1173 t4 write RB_ALPHA_CONTROL (8864)
1174 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
1175 0000000001054748: 0000: 40886401 00000000
1176 t4 write RB_DEPTH_CNTL (8871)
1177 RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER }
1178 0000000001054750: 0000: 48887101 00000000
1179 t4 write RB_STENCIL_CONTROL (8880)
1180 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
1181 0000000001054758: 0000: 40888001 00000000
1182 group_id: 8
1183 count: 7
1184 addr: 0000000001054784
1185 flags: 0
1186 enable_mask: 0x7
1187 0000000001054784: 0000: 40882002 00000780 08040804 40a98901 00000100 48886501 ffff0100
1188 t4 write RB_MRT[0].CONTROL (8820)
1189 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf }
1190 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_SRC_COLOR | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_DST_COLOR | ALPHA_SRC_FACTOR = FACTOR_SRC_COLOR | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_DST_COLOR }
1191 0000000001054784: 0000: 40882002 00000780 08040804
1192 t4 write SP_BLEND_CNTL (a989)
1193 SP_BLEND_CNTL: { UNK8 }
1194 0000000001054790: 0000: 40a98901 00000100
1195 t4 write RB_BLEND_CNTL (8865)
1196 RB_BLEND_CNTL: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff }
1197 0000000001054798: 0000: 48886501 ffff0100
1198 group_id: 19
1199 count: 18
1200 addr: 00000000010546b8
1201 flags: 0
1202 enable_mask: 0x7
1203 00000000010546b8: 0000: 48801086 43000000 43000000 43000000 43000000 00000000 3f800000 4880d002
1204 00000000010546d8: 0020: 00000000 00ff00ff 40800601 0007fdff 48807002 00000000 3f800000 4888c002
1205 00000000010546f8: 0040: 00000000 3f800000
1206 t4 write GRAS_CL_VPORT[0].XOFFSET (8010)
1207 GRAS_CL_VPORT[0].XOFFSET: 128.000000
1208 GRAS_CL_VPORT[0].XSCALE: 128.000000
1209 GRAS_CL_VPORT[0].YOFFSET: 128.000000
1210 GRAS_CL_VPORT[0].YSCALE: 128.000000
1211 GRAS_CL_VPORT[0].ZOFFSET: 0.000000
1212 GRAS_CL_VPORT[0].ZSCALE: 1.000000
1213 00000000010546b8: 0000: 48801086 43000000 43000000 43000000 43000000 00000000 3f800000
1214 t4 write GRAS_SC_VIEWPORT_SCISSOR[0].TL (80d0)
1215 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 }
1216 GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 255 | Y = 255 }
1217 00000000010546d4: 0000: 4880d002 00000000 00ff00ff
1218 t4 write GRAS_CL_GUARDBAND_CLIP_ADJ (8006)
1219 GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 511 | VERT = 511 }
1220 00000000010546e0: 0000: 40800601 0007fdff
1221 t4 write GRAS_CL_Z_CLAMP[0].MIN (8070)
1222 GRAS_CL_Z_CLAMP[0].MIN: 0.000000
1223 GRAS_CL_Z_CLAMP[0].MAX: 1.000000
1224 00000000010546e8: 0000: 48807002 00000000 3f800000
1225 t4 write RB_Z_CLAMP_MIN (88c0)
1226 RB_Z_CLAMP_MIN: 0.000000
1227 RB_Z_CLAMP_MAX: 1.000000
1228 00000000010546f4: 0000: 4888c002 00000000 3f800000
1229 group_id: 20
1230 count: 3
1231 addr: 0000000001054700
1232 flags: 0
1233 enable_mask: 0x7
1234 0000000001054700: 0000: 4880b002 00000000 00ff00ff
1235 t4 write GRAS_SC_SCREEN_SCISSOR[0].TL (80b0)
1236 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 }
1237 GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 255 | Y = 255 }
1238 0000000001054700: 0000: 4880b002 00000000 00ff00ff
1239 group_id: 21
1240 count: 2
1241 addr: 0000000001054730
1242 flags: 0
1243 enable_mask: 0x7
1244 0000000001054730: 0000: 40809001 00000814
1245 t4 write GRAS_SU_CNTL (8090)
1246 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET }
1247 0000000001054730: 0000: 40809001 00000814
1248 group_id: 22
1249 count: 4
1250 addr: 0000000001054738
1251 flags: 0
1252 enable_mask: 0x7
1253 0000000001054738: 0000: 40809583 00000000 00000000 00000000
1254 t4 write GRAS_SU_POLY_OFFSET_SCALE (8095)
1255 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
1256 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
1257 GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000
1258 0000000001054738: 0000: 40809583 00000000 00000000 00000000
1259 group_id: 23
1260 count: 5
1261 addr: 00000000010547a0
1262 flags: 0
1263 enable_mask: 0x7
1264 00000000010547a0: 0000: 48886004 dffe8440 0000ffff dffe8678 0000ffff
1265 t4 write RB_BLEND_RED_F32 (8860)
1266 RB_BLEND_RED_F32: -36679707902607360000.000000
1267 RB_BLEND_GREEN_F32: 0.000000
1268 RB_BLEND_BLUE_F32: -36680956947816513536.000000
1269 RB_BLEND_ALPHA_F32: 0.000000
1270 00000000010547a0: 0000: 48886004 dffe8440 0000ffff dffe8678 0000ffff
1271 group_id: 24
1272 count: 3
1273 addr: 0000000001054760
1274 flags: 0
1275 enable_mask: 0x7
1276 0000000001054760: 0000: 48887802 00000000 00000000
1277 t4 write RB_Z_BOUNDS_MIN (8878)
1278 RB_Z_BOUNDS_MIN: 0.000000
1279 RB_Z_BOUNDS_MAX: 0.000000
1280 0000000001054760: 0000: 48887802 00000000 00000000
1281 group_id: 25
1282 count: 2
1283 addr: 000000000105476c
1284 flags: 0
1285 enable_mask: 0x7
1286 000000000105476c: 0000: 48888801 00000000
1287 t4 write RB_STENCILMASK (8888)
1288 RB_STENCILMASK: { MASK = 0 | BFMASK = 0 }
1289 000000000105476c: 0000: 48888801 00000000
1290 group_id: 26
1291 count: 2
1292 addr: 0000000001054774
1293 flags: 0
1294 enable_mask: 0x7
1295 0000000001054774: 0000: 40888901 00000000
1296 t4 write RB_STENCILWRMASK (8889)
1297 RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 }
1298 0000000001054774: 0000: 40888901 00000000
1299 group_id: 27
1300 count: 2
1301 addr: 000000000105477c
1302 flags: 0
1303 enable_mask: 0x7
1304 000000000105477c: 0000: 48888701 00000000
1305 t4 write RB_STENCILREF (8887)
1306 RB_STENCILREF: { REF = 0 | BFREF = 0 }
1307 000000000105477c: 0000: 48888701 00000000
1308 group_id: 28
1309 count: 6
1310 addr: 00000000010547b4
1311 flags: 0
1312 enable_mask: 0x7
1313 00000000010547b4: 0000: 4880a401 00000000 40880401 00000000 48b30401 00000000
1314 t4 write GRAS_SAMPLE_CONFIG (80a4)
1315 GRAS_SAMPLE_CONFIG: { 0 }
1316 00000000010547b4: 0000: 4880a401 00000000
1317 t4 write RB_SAMPLE_CONFIG (8804)
1318 RB_SAMPLE_CONFIG: { 0 }
1319 00000000010547bc: 0000: 40880401 00000000
1320 t4 write SP_TP_SAMPLE_CONFIG (b304)
1321 SP_TP_SAMPLE_CONFIG: { 0 }
1322 00000000010547c4: 0000: 48b30401 00000000
1323 t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
1324 { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_32_BIT | PATCH_TYPE = TESS_QUADS }
1325 { OPCODE = INDIRECT_OP_INDIRECT_COUNT_INDEXED | DST_OFF = 0 }
1326 { DRAW_COUNT = 3 }
1327 { INDEX = 0x1057000 }
1328 { MAX_INDICES = 9 }
1329 { INDIRECT = 0x1162008 }
1330 { INDIRECT_COUNT = 0x116300c }
1331 { STRIDE = 40 }
1332 mode: RM6_GMEM
1333 skip_ib2: g=0, l=0
1334 indirect count: 2
1335 draw 0:
1336 0000000001162008: 0000: 00000003 00000001 00000002 0000000d 00000000 fffffffc fffffffe fffffff5
1337 0000000001162028: 0020: 00000009 fffffff9 00000003 00000001 00000005 0000000d 00000000 fffffffc
1338 draw 1:
1339 0000000001162030: 0000: 00000003 00000001 00000005 0000000d 00000000 fffffffc fffffffe fffffff5
1340 0000000001162050: 0020: 00000009 fffffff9 fffffffc fffffffe fffffff5 00000009 fffffff9 fffffffc
1341 draw[2] register values
1342 !+ 000000c0 GRAS_CL_CNTL: { ZERO_GB_SCALE_Z | VP_CLIP_CODE_IGNORE }
1343 + 00000000 GRAS_VS_CL_CNTL: { CLIP_MASK = 0 | CULL_MASK = 0 }
1344 + 00000000 GRAS_MAX_LAYER_INDEX: 0
1345 !+ 00000001 GRAS_CNTL: { IJ_PERSP_PIXEL | COORD_MASK = 0 }
1346 !+ 0007fdff GRAS_CL_GUARDBAND_CLIP_ADJ: { HORZ = 511 | VERT = 511 }
1347 !+ 43000000 GRAS_CL_VPORT[0].XOFFSET: 128.000000
1348 !+ 43000000 GRAS_CL_VPORT[0].XSCALE: 128.000000
1349 !+ 43000000 GRAS_CL_VPORT[0].YOFFSET: 128.000000
1350 !+ 43000000 GRAS_CL_VPORT[0].YSCALE: 128.000000
1351 + 00000000 GRAS_CL_VPORT[0].ZOFFSET: 0.000000
1352 !+ 3f800000 GRAS_CL_VPORT[0].ZSCALE: 1.000000
1353 + 00000000 GRAS_CL_Z_CLAMP[0].MIN: 0.000000
1354 !+ 3f800000 GRAS_CL_Z_CLAMP[0].MAX: 1.000000
1355 !+ 00000814 GRAS_SU_CNTL: { FRONT_CW | LINEHALFWIDTH = 0.500000 | POLY_OFFSET }
1356 !+ ffc00001 GRAS_SU_POINT_MINMAX: { MIN = 0.062500 | MAX = 4092.000000 }
1357 !+ 00000010 GRAS_SU_POINT_SIZE: 1.000000
1358 + 00000000 GRAS_SU_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
1359 + 00000000 GRAS_SU_POLY_OFFSET_SCALE: 0.000000
1360 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET: 0.000000
1361 + 00000000 GRAS_SU_POLY_OFFSET_OFFSET_CLAMP: 0.000000
1362 + 00000000 GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
1363 + 00000000 GRAS_VS_LAYER_CNTL: { 0 }
1364 + 00000000 GRAS_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
1365 !+ 00000004 GRAS_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
1366 + 00000000 GRAS_SAMPLE_CONFIG: { 0 }
1367 + 00000000 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 }
1368 !+ 00ff00ff GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 255 | Y = 255 }
1369 + 00000000 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 }
1370 !+ 00ff00ff GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 255 | Y = 255 }
1371 + 00000000 GRAS_UNKNOWN_8101: 0
1372 + 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0
1373 + 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
1374 + 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
1375 + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
1376 + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
1377 + 00000000 GRAS_SAMPLE_CNTL: { 0 }
1378 !+ 00010010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0x1 }
1379 + 00000000 RB_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
1380 !+ 00000004 RB_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
1381 + 00000000 RB_SAMPLE_CONFIG: { 0 }
1382 + 00000401 RB_RENDER_CONTROL0: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 }
1383 + 00000000 RB_RENDER_CONTROL1: { 0 }
1384 + 00000000 RB_FS_OUTPUT_CNTL0: { 0 }
1385 !+ 00000001 RB_FS_OUTPUT_CNTL1: { MRT = 1 }
1386 !+ 0000000f RB_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
1387 + 00000000 RB_SRGB_CNTL: { 0 }
1388 + 00000000 RB_SAMPLE_CNTL: { 0 }
1389 !+ 00000780 RB_MRT[0].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0xf }
1390 !+ 08040804 RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_SRC_COLOR | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_DST_COLOR | ALPHA_SRC_FACTOR = FACTOR_SRC_COLOR | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_DST_COLOR }
1391 !+ 00000330 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX }
1392 !+ 00000010 RB_MRT[0].PITCH: 1024
1393 !+ 00001000 RB_MRT[0].ARRAY_PITCH: 262144
1394 !+ 01013000 RB_MRT[0].BASE_LO: 0x1013000
1395 + 00000000 RB_MRT[0].BASE_HI: 0
1396 + 00000000 RB_MRT[0].BASE_GMEM: 0
1397 !+ dffe8440 RB_BLEND_RED_F32: -36679707902607360000.000000
1398 !+ 0000ffff RB_BLEND_GREEN_F32: 0.000000
1399 !+ dffe8678 RB_BLEND_BLUE_F32: -36680956947816513536.000000
1400 !+ 0000ffff RB_BLEND_ALPHA_F32: 0.000000
1401 + 00000000 RB_ALPHA_CONTROL: { ALPHA_REF = 0 | ALPHA_TEST_FUNC = FUNC_NEVER }
1402 !+ ffff0100 RB_BLEND_CNTL: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff }
1403 + 00000000 RB_DEPTH_PLANE_CNTL: { Z_MODE = A6XX_EARLY_Z }
1404 + 00000000 RB_DEPTH_CNTL: { ZFUNC = FUNC_NEVER }
1405 + 00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
1406 + 00000000 RB_DEPTH_BUFFER_PITCH: 0
1407 + 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0
1408 + 00000000 RB_DEPTH_BUFFER_BASE_LO: 0
1409 + 00000000 RB_DEPTH_BUFFER_BASE_HI: 0
1410 + 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0
1411 + 00000000 RB_Z_BOUNDS_MIN: 0.000000
1412 + 00000000 RB_Z_BOUNDS_MAX: 0.000000
1413 + 00000000 RB_STENCIL_CONTROL: { FUNC = FUNC_NEVER | FAIL = STENCIL_KEEP | ZPASS = STENCIL_KEEP | ZFAIL = STENCIL_KEEP | FUNC_BF = FUNC_NEVER | FAIL_BF = STENCIL_KEEP | ZPASS_BF = STENCIL_KEEP | ZFAIL_BF = STENCIL_KEEP }
1414 + 00000000 RB_STENCIL_INFO: { 0 }
1415 + 00000000 RB_STENCILREF: { REF = 0 | BFREF = 0 }
1416 + 00000000 RB_STENCILMASK: { MASK = 0 | BFMASK = 0 }
1417 + 00000000 RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 }
1418 + 00000000 RB_Z_CLAMP_MIN: 0.000000
1419 !+ 3f800000 RB_Z_CLAMP_MAX: 1.000000
1420 + 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
1421 + 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
1422 + 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
1423 !+ 01012000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0x1012000
1424 + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
1425 !+ 00004001 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
1426 !+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
1427 !+ 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
1428 !+ 00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
1429 + 00000000 VPC_VARYING_INTERP[0].MODE: 0
1430 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0
1431 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0
1432 + 00000000 VPC_VARYING_INTERP[0x3].MODE: 0
1433 + 00000000 VPC_VARYING_INTERP[0x4].MODE: 0
1434 + 00000000 VPC_VARYING_INTERP[0x5].MODE: 0
1435 + 00000000 VPC_VARYING_INTERP[0x6].MODE: 0
1436 + 00000000 VPC_VARYING_INTERP[0x7].MODE: 0
1437 + 00000000 VPC_VARYING_PS_REPL[0].MODE: 0
1438 + 00000000 VPC_VARYING_PS_REPL[0x1].MODE: 0
1439 + 00000000 VPC_VARYING_PS_REPL[0x2].MODE: 0
1440 + 00000000 VPC_VARYING_PS_REPL[0x3].MODE: 0
1441 + 00000000 VPC_VARYING_PS_REPL[0x4].MODE: 0
1442 + 00000000 VPC_VARYING_PS_REPL[0x5].MODE: 0
1443 + 00000000 VPC_VARYING_PS_REPL[0x6].MODE: 0
1444 + 00000000 VPC_VARYING_PS_REPL[0x7].MODE: 0
1445 !+ fffffff0 VPC_VAR[0].DISABLE: 0xfffffff0
1446 !+ ffffffff VPC_VAR[0x1].DISABLE: 0xffffffff
1447 !+ ffffffff VPC_VAR[0x2].DISABLE: 0xffffffff
1448 !+ ffffffff VPC_VAR[0x3].DISABLE: 0xffffffff
1449 + 00000000 VPC_SO_CNTL: { 0 }
1450 !+ 00ff0408 VPC_VS_PACK: { STRIDE_IN_VPC = 8 | POSITIONLOC = 4 | PSIZELOC = 255 }
1451 !+ ff01ff04 VPC_CNTL_0: { NUMNONPOSVAR = 4 | PRIMIDLOC = 255 | VARYING | UNKLOC = 255 }
1452 + 00000000 VPC_SO_BUF_CNTL: { 0 }
1453 !+ ffffffff PC_RESTART_INDEX: 4294967295
1454 + 00000000 PC_PRIMID_PASSTHRU: FALSE
1455 !+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES }
1456 + 00000000 PC_PRIMITIVE_CNTL_0: { 0 }
1457 !+ 00000008 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 8 | CLIP_MASK = 0 }
1458 !+ 00000303 VFD_CONTROL_0: { FETCH_CNT = 3 | DECODE_CNT = 3 }
1459 !+ fcfcfc09 VFD_CONTROL_1: { REGID4VTX = r2.y | REGID4INST = r63.x | REGID4PRIMID = r63.x | 0xfc000000 }
1460 !+ 0000fcfc VFD_CONTROL_2: { REGID_HSPATCHID = r63.x | REGID_INVOCATIONID = r63.x }
1461 !+ fcfcfcfc VFD_CONTROL_3: { REGID_DSPATCHID = r63.x | REGID_TESSX = r63.x | REGID_TESSY = r63.x | 0xfc }
1462 !+ 000000fc VFD_CONTROL_4: 0xfc
1463 !+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 }
1464 + 00000000 VFD_CONTROL_6: { 0 }
1465 !+ 01053000 VFD_FETCH[0].BASE: 0x1053000
1466 + 00000000 VFD_FETCH[0].BASE+0x1: 0
1467 !+ 00000318 VFD_FETCH[0].SIZE: 792
1468 !+ 00000024 VFD_FETCH[0].STRIDE: 36
1469 !+ c8200000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
1470 !+ 00000001 VFD_DECODE[0].STEP_RATE: 0x1
1471 !+ c8200200 VFD_DECODE[0x1].INSTR: { IDX = 0 | OFFSET = 0x10 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
1472 !+ 00000001 VFD_DECODE[0x1].STEP_RATE: 0x1
1473 !+ 44c00400 VFD_DECODE[0x2].INSTR: { IDX = 0 | OFFSET = 0x20 | FORMAT = FMT6_32_SINT | SWAP = WZYX | UNK30 }
1474 !+ 00000001 VFD_DECODE[0x2].STEP_RATE: 0x1
1475 !+ 0000000f VFD_DEST_CNTL[0].INSTR: { WRITEMASK = 0xf | REGID = r0.x }
1476 !+ 0000004f VFD_DEST_CNTL[0x1].INSTR: { WRITEMASK = 0xf | REGID = r1.x }
1477 !+ 00000081 VFD_DEST_CNTL[0x2].INSTR: { WRITEMASK = 0x1 | REGID = r2.x }
1478 !+ 80100180 SP_VS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 3 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | MERGEDREGS }
1479 !+ 00000002 SP_VS_PRIMITIVE_CNTL: { OUT = 2 }
1480 !+ 0f000f08 SP_VS_OUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf }
1481 !+ 00000400 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 0 | OUTLOC3 = 0 }
1482 !+ 01054000 SP_VS_OBJ_START_LO: 0x1054000 base=1054000, offset=0, size=12288
1483 + 00000000 SP_VS_OBJ_START_HI: 0 base=1054000, offset=0, size=12288
1484 0000000001054000: 0000: 00080009 42bc080b 10040004 64858008 10050005 64858009 10050006 6485800a
1485 0000000001054020: 0020: 10040007 6485800b 00000000 03000000 00000000 00000000 00000000 00000000
1486 *
1487 0000000001054080: 0080: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005
1488 00000000010540a0: 00a0: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
1489 *
1490 :2:0000:0000[42bc080bx_00080009x] (nop3) cmps.s.eq r2.w, r2.y, r2.x
1491 :3:0001:0004[64858008x_10040004x] sel.b32 r2.x, r1.x, r2.w, c1.x
1492 :3:0002:0005[64858009x_10050005x] sel.b32 r2.y, r1.y, r2.w, c1.y
1493 :3:0003:0006[6485800ax_10050006x] sel.b32 r2.z, r1.z, r2.w, c1.y
1494 :3:0004:0007[6485800bx_10040007x] sel.b32 r2.w, r1.w, r2.w, c1.x
1495 :0:0005:0008[03000000x_00000000x] end
1496 :0:0006:0009[00000000x_00000000x] nop
1497 :0:0007:0010[00000000x_00000000x] nop
1498 :0:0008:0011[00000000x_00000000x] nop
1499 :0:0009:0012[00000000x_00000000x] nop
1500 Register Stats:
1501 - used (half): 8-23 (cnt=16, max=23)
1502 - used (full): 4-11 (cnt=8, max=11)
1503 - input (half): 8-19 (cnt=12, max=19)
1504 - input (full): 4-9 (cnt=6, max=9)
1505 - max const: 5
1506
1507 - output (half): 16-23 (cnt=8, max=23) (estimated)
1508 - output (full): 8-11 (cnt=4, max=11) (estimated)
1509 - shaderdb: 13 instructions, 7 nops, 6 non-nops, (10 instlen), 0 last-baryf, 0 half, 3 full
1510 - shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
1511 - shaderdb: 0 (ss), 0 (sy)
1512 !+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
1513 !+ 00000001 SP_VS_INSTRLEN: 1
1514 + 00000000 SP_HS_UNKNOWN_A831: 0
1515 + 00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
1516 + 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
1517 + 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
1518 !+ 81500100 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 | THREADSIZE = FOUR_QUADS | VARYING | MERGEDREGS | 0x1000000 }
1519 !+ 01054080 SP_FS_OBJ_START_LO: 0x1054080 base=1054000, offset=128, size=12288
1520 + 00000000 SP_FS_OBJ_START_HI: 0 base=1054000, offset=128, size=12288
1521 0000000001054080: 0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005
1522 00000000010540a0: 0020: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
1523 *
1524 0000000001054100: 0080: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
1525 *
1526 :2:0000:0000[47300002x_00002000x] bary.f r0.z, 0, r0.x
1527 :2:0001:0001[47300003x_00002001x] bary.f r0.w, 1, r0.x
1528 :2:0002:0002[47300004x_00002002x] bary.f r1.x, 2, r0.x
1529 :2:0003:0003[47308005x_00002003x] bary.f (ei)r1.y, 3, r0.x
1530 :0:0004:0004[03000000x_00000000x] end
1531 :0:0005:0005[00000000x_00000000x] nop
1532 :0:0006:0006[00000000x_00000000x] nop
1533 :0:0007:0007[00000000x_00000000x] nop
1534 :0:0008:0008[00000000x_00000000x] nop
1535 Register Stats:
1536 - used (half): 0-1 4-11 (cnt=10, max=11)
1537 - used (full): 0 2-5 (cnt=5, max=5)
1538 - input (half): 0-1 (cnt=2, max=1)
1539 - input (full): 0 (cnt=1, max=0)
1540 - max const: 0
1541
1542 - output (half): 4-11 (cnt=8, max=11) (estimated)
1543 - output (full): 2-5 (cnt=4, max=5) (estimated)
1544 - shaderdb: 9 instructions, 4 nops, 5 non-nops, (9 instlen), 3 last-baryf, 0 half, 2 full
1545 - shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
1546 - shaderdb: 0 (ss), 0 (sy)
1547 !+ 00000100 SP_BLEND_CNTL: { UNK8 }
1548 + 00000000 SP_SRGB_CNTL: { 0 }
1549 !+ 0000000f SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
1550 !+ fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
1551 !+ 00000001 SP_FS_OUTPUT_CNTL1: { MRT = 1 }
1552 !+ 00000002 SP_FS_OUTPUT[0].REG: { REGID = r0.z }
1553 !+ 000000fc SP_FS_OUTPUT[0x1].REG: { REGID = r63.x }
1554 !+ 000000fc SP_FS_OUTPUT[0x2].REG: { REGID = r63.x }
1555 !+ 000000fc SP_FS_OUTPUT[0x3].REG: { REGID = r63.x }
1556 !+ 000000fc SP_FS_OUTPUT[0x4].REG: { REGID = r63.x }
1557 !+ 000000fc SP_FS_OUTPUT[0x5].REG: { REGID = r63.x }
1558 !+ 000000fc SP_FS_OUTPUT[0x6].REG: { REGID = r63.x }
1559 !+ 000000fc SP_FS_OUTPUT[0x7].REG: { REGID = r63.x }
1560 !+ 00000030 SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
1561 !+ 00007fc0 SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 }
1562 + 00000000 SP_CS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
1563 !+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
1564 !+ 00000001 SP_FS_INSTRLEN: 1
1565 + 00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
1566 !+ 00000004 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE | MSAA_DISABLE }
1567 + 00000000 SP_TP_SAMPLE_CONFIG: { 0 }
1568 !+ 00000101 HLSQ_VS_CNTL: { CONSTLEN = 4 | ENABLED }
1569 + 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 }
1570 + 00000000 HLSQ_DS_CNTL: { CONSTLEN = 0 }
1571 + 00000000 HLSQ_GS_CNTL: { CONSTLEN = 0 }
1572 !+ 00000003 HLSQ_UNKNOWN_B980: 0x3
1573 !+ 00000007 HLSQ_CONTROL_1_REG: 0x7
1574 !+ fcfcfcfc HLSQ_CONTROL_2_REG: { FACEREGID = r63.x | SAMPLEID = r63.x | SAMPLEMASK = r63.x | SIZE = r63.x }
1575 !+ fcfcfc00 HLSQ_CONTROL_3_REG: { IJ_PERSP_PIXEL = r0.x | IJ_LINEAR_PIXEL = r63.x | IJ_PERSP_CENTROID = r63.x | IJ_LINEAR_CENTROID = r63.x }
1576 !+ fcfcfcfc HLSQ_CONTROL_4_REG: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
1577 + 000000fc HLSQ_CONTROL_5_REG: 0xfc
1578 + 00000000 HLSQ_CS_CNTL: { CONSTLEN = 0 }
1579 !+ 0000009f HLSQ_INVALIDATE_CMD: { VS_STATE | HS_STATE | DS_STATE | GS_STATE | FS_STATE | GFX_IBO | CS_BINDLESS = 0 | GFX_BINDLESS = 0 }
1580 !+ 00000100 HLSQ_FS_CNTL: { CONSTLEN = 0 | ENABLED }
1581 000000000115e394: 0000: 702a000b 00000904 00000007 00000003 01057000 00000000 00000009 01162008
1582 000000000115e3b4: 0020: 00000000 0116300c 00000000 00000028
1583 00000000010583b8: 0000: 70bf8003 0115e000 00000000 000000f1
1584 t7 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1585 ibaddr:000000000115c000
1586 ibsize:0000001c
1587 t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords)
1588 { COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
1589 { ADDR_LO = 0 }
1590 { ADDR_HI = 0 }
1591 000000000115c000: 0000: 70438003 00040000 00000000 00000000
1592 t7 opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
1593 000000000115c010: 0000: 709d0001 00000000
1594 t7 opcode: CP_SET_MARKER (65) (2 dwords)
1595 { MODE = RM6_RESOLVE | MARKER = RM6_RESOLVE }
1596 000000000115c018: 0000: 70e50001 00000006
1597 t4 write RB_BLIT_SCISSOR_TL (88d1)
1598 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
1599 RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
1600 000000000115c020: 0000: 4888d102 00000000 00ff00ff
1601 t4 write RB_MSAA_CNTL (88d5)
1602 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
1603 000000000115c02c: 0000: 4088d501 00000000
1604 t4 write RB_BLIT_INFO (88e3)
1605 RB_BLIT_INFO: { CLEAR_MASK = 0 }
1606 000000000115c034: 0000: 4088e301 00000000
1607 t4 write RB_BLIT_DST_INFO (88d7)
1608 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
1609 RB_BLIT_DST: 0x1013000
1610 RB_BLIT_DST+0x1: 0
1611 RB_BLIT_DST_PITCH: 1024
1612 000000000115c03c: 0000: 4888d704 00001807 01013000 00000000 00000010
1613 t4 write RB_BLIT_FLAG_DST (88dc)
1614 RB_BLIT_FLAG_DST: 0x1012000
1615 RB_BLIT_FLAG_DST+0x1: 0
1616 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
1617 000000000115c050: 0000: 4088dc83 01012000 00000000 00004001
1618 t4 write RB_BLIT_BASE_GMEM (88d6)
1619 RB_BLIT_BASE_GMEM: 0
1620 000000000115c060: 0000: 4088d601 00000000
1621 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
1622 { EVENT = BLIT }
1623 event BLIT
1624 mode: RM6_RESOLVE
1625 skip_ib2: g=0, l=0
1626 draw[3] register values
1627 + 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
1628 + 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
1629 + 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
1630 + 00000000 RB_BLIT_BASE_GMEM: 0
1631 + 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
1632 + 01013000 RB_BLIT_DST: 0x1013000
1633 + 00000000 RB_BLIT_DST+0x1: 0
1634 + 00000010 RB_BLIT_DST_PITCH: 1024
1635 + 01012000 RB_BLIT_FLAG_DST: 0x1012000
1636 + 00000000 RB_BLIT_FLAG_DST+0x1: 0
1637 + 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
1638 !+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 }
1639 000000000115c068: 0000: 70460001 0000001e
1640 00000000010583c8: 0000: 70bf8003 0115c000 00000000 0000001c
1641 t4 write GRAS_LRZ_CNTL (8100)
1642 GRAS_LRZ_CNTL: { 0 }
1643 00000000010583d8: 0000: 48810001 00000000
1644 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
1645 { EVENT = LRZ_FLUSH }
1646 event LRZ_FLUSH
1647 00000000010583e0: 0000: 70460001 00000026
1648 t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
1649 { EVENT = PC_CCU_RESOLVE_TS }
1650 { ADDR_0_LO = 0x1011880 }
1651 { ADDR_0_HI = 0 }
1652 { 3 = 0 }
1653 event PC_CCU_RESOLVE_TS
1654 00000000010583e8: 0000: 70460004 0000001a 01011880 00000000 00000000
1655 t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
1656 { EVENT = PC_CCU_FLUSH_COLOR_TS }
1657 { ADDR_0_LO = 0x1011880 }
1658 { ADDR_0_HI = 0 }
1659 { 3 = 0 }
1660 event PC_CCU_FLUSH_COLOR_TS
1661 00000000010583fc: 0000: 70460004 0000001d 01011880 00000000 00000000
1662 t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
1663 { EVENT = PC_CCU_FLUSH_DEPTH_TS }
1664 { ADDR_0_LO = 0x1011880 }
1665 { ADDR_0_HI = 0 }
1666 { 3 = 0 }
1667 event PC_CCU_FLUSH_DEPTH_TS
1668 0000000001058410: 0000: 70460004 0000001c 01011880 00000000 00000000
1669 ############################################################
1670 vertices: 0
1671 cmd: deqp-vk/74711: fence=247338