Return-path: <libre-riscv-dev-bounces@lists.libre-riscv.org>
Envelope-to: publicinbox@libre-riscv.org
Delivery-date: Fri, 27 Mar 2020 09:08:59 +0000
Received: from localhost ([::1] helo=libre-riscv.org)
	by libre-riscv.org with esmtp (Exim 4.89)
	(envelope-from <libre-riscv-dev-bounces@lists.libre-riscv.org>)
	id 1jHkz4-0002mT-PM; Fri, 27 Mar 2020 09:08:58 +0000
Received: from vps2.stafverhaegen.be ([85.10.201.15])
 by libre-riscv.org with esmtp (Exim 4.89)
 (envelope-from <staf@fibraservi.eu>) id 1jHkz3-0002mN-F8
 for libre-riscv-dev@lists.libre-riscv.org; Fri, 27 Mar 2020 09:08:57 +0000
Received: from hpdc7800 (hpdc7800 [10.0.0.1])
 by vps2.stafverhaegen.be (Postfix) with ESMTP id A6F9711C05D7
 for <libre-riscv-dev@lists.libre-riscv.org>;
 Fri, 27 Mar 2020 10:08:56 +0100 (CET)
Message-ID: <65e762e270e3660044604cc48f4fbd554d34af13.camel@fibraservi.eu>
From: Staf Verhaegen <staf@fibraservi.eu>
To: libre-riscv-dev@lists.libre-riscv.org
Date: Fri, 27 Mar 2020 10:08:48 +0100
In-Reply-To: <CAPweEDx9YH=0DWviRYJySR9++n-Nd88ZHkRb8EkWhah3x4MbeQ@mail.gmail.com>
References: <CAPweEDx5QCCKxSr1gfuyuw_2D68Ld8fK85bEmmMTZi8S3w2E9g@mail.gmail.com>
 <29b1a9ecedda151dc9c8da6516c3691dfede62ef.camel@fibraservi.eu>
 <CAPweEDwfqMczPjg=5Fvt1J_S8nx1YK44XhyBY8H1abuTNF6=xg@mail.gmail.com>
 <6fa40cb78b3f8c013ca4953ccb4daa5c23e3b501.camel@fibraservi.eu>
 <CAPweEDxiyTEsneXN65Kq0HsEsdL3wdY=NYayq2tz5egXJNCVfg@mail.gmail.com>
 <db557324bcb76a999d8f66c75b9319974a1a1e08.camel@fibraservi.eu>
 <CAPweEDyM_wqTbum5+=iiLGqq3KY15OOg3aOewpsRWFp9iOvq0w@mail.gmail.com>
 <7b5a312befec67dbf14d31f5bb4c418c8784e787.camel@fibraservi.eu>
 <CAPweEDx9YH=0DWviRYJySR9++n-Nd88ZHkRb8EkWhah3x4MbeQ@mail.gmail.com>
Organization: FibraServi bvba
X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) 
Mime-Version: 1.0
X-Content-Filtered-By: Mailman/MimeDel 2.1.23
Subject: Re: [libre-riscv-dev] cache SRAM organisation
X-BeenThere: libre-riscv-dev@lists.libre-riscv.org
X-Mailman-Version: 2.1.23
Precedence: list
List-Id: Libre-RISCV General Development
 <libre-riscv-dev.lists.libre-riscv.org>
List-Unsubscribe: <http://lists.libre-riscv.org/mailman/options/libre-riscv-dev>, 
 <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=unsubscribe>
List-Archive: <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
List-Post: <mailto:libre-riscv-dev@lists.libre-riscv.org>
List-Help: <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=help>
List-Subscribe: <http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev>, 
 <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=subscribe>
Reply-To: Libre-RISCV General Development
 <libre-riscv-dev@lists.libre-riscv.org>
Content-Type: multipart/mixed; boundary="===============5165738825248516375=="
Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org
Sender: "libre-riscv-dev" <libre-riscv-dev-bounces@lists.libre-riscv.org>


--===============5165738825248516375==
Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature";
	boundary="=-fd14a8lsm1mnd74j+5HY"


--=-fd14a8lsm1mnd74j+5HY
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 21:28 [+0000]:
> On Thu, Mar 26, 2020 at 8:08 PM Staf Verhaegen <staf@fibraservi.eu> wrote=
:
> > Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 15:15 [+0000]:
> > > On Thursday, March 26, 2020, Staf Verhaegen <staf@fibraservi.eu> wrot=
e:
> > > > I can understand you do this to implement functional units withconf=
igurable pipeline length but I would strongly discourage to pipelineregiste=
r files after each other .
> > >=20
> > >=20
> > > "pipeline register files after each other"? apologies i am not clear =
whatyou mean, here.  do you mean "don't do write-thru on the Regfile"?
> >=20
> > No I meant for example connecting the output of one port of an asynchro=
nous RAM to for example the address input of another port of an asynchronou=
s RAM.
>=20
> ah right, no definitely not.  the connections are:
> RegisterFile readport[0..R] =3D=3D> FunctionUnit[0..M] operand latches   =
                                         pipeline stage 0                  =
                          pipeline stage 1                                 =
           ...                                            pipeline stage NR=
egisterFile writeport[0..W] <=3D=3D FunctionUnit[0..M] result latches
> (and also: )register file bypass forwardingbus <=3D=3D FunctionUnit resul=
t latchesregister file bypass forwardingbus =3D=3D> FunctionUnit operand la=
tches
> so the asynchronous SRAMs will definitely *only* be connected to SFFlatch=
es.  *not* to other asynchronous SRAMs.

I still feel you intermix synchronous and write-through in this statement, =
the above seems to be possible with synchronous SRAMs.

greets,
Staf.


--=-fd14a8lsm1mnd74j+5HY--



--===============5165738825248516375==
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: base64
Content-Disposition: inline

X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz
Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn
Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj
di1kZXYK

--===============5165738825248516375==--