# Pinouts (PinMux)
auto-generated by [[pinouts.py]]

[[!toc  ]]


## Bank N (32 pins, width 2)

| Pin | Mux0        | Mux1        | Mux2        | Mux3        |
| --- | ----------- | ----------- | ----------- | ----------- |
|   0 | N VSSE_6    |             |
|   1 | N VDDE_6    |             |
|   2 | N VDDI_6    |             |
|   3 | N VSSI_6    |             |
|  23 | N SYS_RST   |             |
|  24 | N SYS_PLLSELA0 |             |
|  25 | N SYS_PLLSELA1 |             |
|  26 | N SYS_PLLCLK |             |
|  27 | N SYS_PLLTESTOUT |             |
|  28 | N VSSI_7    |             |
|  29 | N VDDI_7    |             |
|  30 | N VSSI_7    |             |
|  31 | N VDDI_7    |             |

## Bank E (32 pins, width 2)

| Pin | Mux0        | Mux1        | Mux2        | Mux3        |
| --- | ----------- | ----------- | ----------- | ----------- |
|  32 | E VSSI_4    |             |
|  33 | E VDDI_4    |             |
|  34 | E VDDI_4    |             |
|  35 | E VSSI_4    |             |
|  36 | E SYS_PLLVCOUT |             |
|  37 | E MSPI0_CK  |             |
|  38 | E MSPI0_NSS |             |
|  39 | E MSPI0_MOSI |             |
|  40 | E MSPI0_MISO |             |
|  41 | E GPIOE_E0  |             |
|  42 | E GPIOE_E1  |             |
|  43 | E GPIOE_E2  |             |
|  44 | E GPIOE_E3  |             |
|  45 | E GPIOE_E4  |             |
|  46 | E GPIOE_E5  |             |
|  47 | E GPIOE_E6  |             |
|  48 | E GPIOE_E7  |             |
|  49 | E GPIOE_E8  |             |
|  50 | E GPIOE_E9  |             |
|  51 | E GPIOE_E10 |             |
|  52 | E GPIOE_E11 |             |
|  53 | E GPIOE_E12 |             |
|  54 | E GPIOE_E13 |             |
|  55 | E GPIOE_E14 |             |
|  56 | E GPIOE_E15 |             |
|  57 | E EINT_0    |             |
|  58 | E EINT_1    |             |
|  59 | E EINT_2    |             |
|  60 | E VSSI_5    |             |
|  61 | E VDDI_5    |             |
|  62 | E VSSI_5    |             |
|  63 | E VDDI_5    |             |

## Bank S (32 pins, width 2)

| Pin | Mux0        | Mux1        | Mux2        | Mux3        |
| --- | ----------- | ----------- | ----------- | ----------- |
|  64 | S VDDE_0    |             |
|  65 | S VSSE_0    |             |
|  66 | S VDDI_0    |             |
|  67 | S VSSI_0    |             |
|  68 | S SDR_DQM0  |             |
|  69 | S SDR_D0    |             |
|  70 | S SDR_D1    |             |
|  71 | S SDR_D2    |             |
|  72 | S SDR_D3    |             |
|  73 | S SDR_D4    |             |
|  74 | S SDR_D5    |             |
|  75 | S SDR_D6    |             |
|  76 | S SDR_D7    |             |
|  77 | S SDR_AD0   |             |
|  78 | S SDR_AD1   |             |
|  79 | S SDR_AD2   |             |
|  80 | S SDR_AD3   |             |
|  81 | S SDR_AD4   |             |
|  82 | S SDR_AD5   |             |
|  83 | S SDR_AD6   |             |
|  84 | S SDR_AD7   |             |
|  85 | S SDR_AD8   |             |
|  86 | S SDR_AD9   |             |
|  87 | S SDR_BA0   |             |
|  88 | S SDR_BA1   |             |
|  90 | S MTWI_SDA  |             |
|  91 | S MTWI_SCL  |             |
|  92 | S VSSI_1    |             |
|  93 | S VDDI_1    |             |
|  94 | S VSSE_1    |             |
|  95 | S VDDE_1    |             |

## Bank W (32 pins, width 2)

| Pin | Mux0        | Mux1        | Mux2        | Mux3        |
| --- | ----------- | ----------- | ----------- | ----------- |
|  96 | W VDDE_2    |             |
|  97 | W VSSE_2    |             |
|  98 | W VDDI_2    |             |
|  99 | W VSSI_2    |             |
| 100 | W SDR_AD10  |             |
| 101 | W SDR_AD11  |             |
| 102 | W SDR_AD12  |             |
| 103 | W SDR_DQM1  |             |
| 104 | W SDR_D8    |             |
| 105 | W SDR_D9    |             |
| 106 | W SDR_D10   |             |
| 107 | W SDR_D11   |             |
| 108 | W SDR_D12   |             |
| 109 | W SDR_D13   |             |
| 110 | W SDR_D14   |             |
| 111 | W SDR_D15   |             |
| 112 | W SDR_CLK   |             |
| 113 | W SDR_CKE   |             |
| 114 | W SDR_RASn  |             |
| 115 | W SDR_CASn  |             |
| 116 | W SDR_WEn   |             |
| 117 | W SDR_CSn0  |             |
| 118 | W UART0_TX  |             |
| 119 | W UART0_RX  |             |
| 120 | W JTAG_TMS  |             |
| 121 | W JTAG_TDI  |             |
| 122 | W JTAG_TDO  |             |
| 123 | W JTAG_TCK  |             |
| 124 | W VSSI_3    |             |
| 125 | W VDDI_3    |             |
| 126 | W VSSE_3    |             |
| 127 | W VDDE_3    |             |

# Pinouts (Fixed function)

# Functions (PinMux)

auto-generated by [[pinouts.py]]

## EINT

External Interrupt

* EINT_0    : E25/0
* EINT_1    : E26/0
* EINT_2    : E27/0

## GPIO

GPIO

* GPIOE_E0  : E9/0
* GPIOE_E1  : E10/0
* GPIOE_E10 : E19/0
* GPIOE_E11 : E20/0
* GPIOE_E12 : E21/0
* GPIOE_E13 : E22/0
* GPIOE_E14 : E23/0
* GPIOE_E15 : E24/0
* GPIOE_E2  : E11/0
* GPIOE_E3  : E12/0
* GPIOE_E4  : E13/0
* GPIOE_E5  : E14/0
* GPIOE_E6  : E15/0
* GPIOE_E7  : E16/0
* GPIOE_E8  : E17/0
* GPIOE_E9  : E18/0

## JTAG

JTAG

* JTAG_TCK  : W27/0
* JTAG_TDI  : W25/0
* JTAG_TDO  : W26/0
* JTAG_TMS  : W24/0

## MSPI0

SPI Master 1 (general)

* MSPI0_CK  : E5/0
* MSPI0_MISO : E8/0
* MSPI0_MOSI : E7/0
* MSPI0_NSS : E6/0

## MTWI

I2C Master 1

* MTWI_SCL  : S27/0
* MTWI_SDA  : S26/0

## SDR

SDRAM

* SDR_AD0   : S13/0
* SDR_AD1   : S14/0
* SDR_AD10  : W4/0
* SDR_AD11  : W5/0
* SDR_AD12  : W6/0
* SDR_AD2   : S15/0
* SDR_AD3   : S16/0
* SDR_AD4   : S17/0
* SDR_AD5   : S18/0
* SDR_AD6   : S19/0
* SDR_AD7   : S20/0
* SDR_AD8   : S21/0
* SDR_AD9   : S22/0
* SDR_BA0   : S23/0
* SDR_BA1   : S24/0
* SDR_CASn  : W19/0
* SDR_CKE   : W17/0
* SDR_CLK   : W16/0
* SDR_CSn0  : W21/0
* SDR_D0    : S5/0
* SDR_D1    : S6/0
* SDR_D10   : W10/0
* SDR_D11   : W11/0
* SDR_D12   : W12/0
* SDR_D13   : W13/0
* SDR_D14   : W14/0
* SDR_D15   : W15/0
* SDR_D2    : S7/0
* SDR_D3    : S8/0
* SDR_D4    : S9/0
* SDR_D5    : S10/0
* SDR_D6    : S11/0
* SDR_D7    : S12/0
* SDR_D8    : W8/0
* SDR_D9    : W9/0
* SDR_DQM0  : S4/0
* SDR_DQM1  : W7/0
* SDR_RASn  : W18/0
* SDR_WEn   : W20/0

## SYS

System Control

* SYS_PLLCLK : N26/0
* SYS_PLLSELA0 : N24/0
* SYS_PLLSELA1 : N25/0
* SYS_PLLTESTOUT : N27/0
* SYS_PLLVCOUT : E4/0
* SYS_RST   : N23/0

## UART0

UART (TX/RX) 1

* UART0_RX  : W23/0
* UART0_TX  : W22/0

## VDD

Power

* VDDE_0    : S0/0
* VDDE_1    : S31/0
* VDDE_2    : W0/0
* VDDE_3    : W31/0
* VDDE_6    : N1/0
* VDDI_0    : S2/0
* VDDI_1    : S29/0
* VDDI_2    : W2/0
* VDDI_3    : W29/0
* VDDI_4    : E1/0 E2/0
* VDDI_5    : E29/0 E31/0
* VDDI_6    : N2/0
* VDDI_7    : N29/0 N31/0

## VSS

GND

* VSSE_0    : S1/0
* VSSE_1    : S30/0
* VSSE_2    : W1/0
* VSSE_3    : W30/0
* VSSE_6    : N0/0
* VSSI_0    : S3/0
* VSSI_1    : S28/0
* VSSI_2    : W3/0
* VSSI_3    : W28/0
* VSSI_4    : E0/0 E3/0
* VSSI_5    : E28/0 E30/0
* VSSI_6    : N3/0
* VSSI_7    : N28/0 N30/0

# Pinmap for Libre-SOC 180nm

## UART0



* UART0_TX 118 W22/0
* UART0_RX 119 W23/0

## GPIOS


## GPIOE

* GPIOE_E0 41 E9/0
* GPIOE_E1 42 E10/0
* GPIOE_E2 43 E11/0
* GPIOE_E3 44 E12/0
* GPIOE_E4 45 E13/0
* GPIOE_E5 46 E14/0
* GPIOE_E6 47 E15/0
* GPIOE_E7 48 E16/0
* GPIOE_E8 49 E17/0
* GPIOE_E9 50 E18/0
* GPIOE_E10 51 E19/0
* GPIOE_E11 52 E20/0
* GPIOE_E12 53 E21/0
* GPIOE_E13 54 E22/0
* GPIOE_E14 55 E23/0
* GPIOE_E15 56 E24/0

## JTAG

* JTAG_TMS 120 W24/0
* JTAG_TDI 121 W25/0
* JTAG_TDO 122 W26/0
* JTAG_TCK 123 W27/0

## PWM


## EINT

* EINT_0 57 E25/0
* EINT_1 58 E26/0
* EINT_2 59 E27/0

## VDD

* VDDE_6 1 N1/0
* VDDI_6 2 N2/0
* VDDI_7 29 N29/0
* VDDI_4 33 E1/0
* VDDI_5 61 E29/0

## VSS

* VSSE_6 0 N0/0
* VSSI_6 3 N3/0
* VSSI_7 28 N28/0
* VSSI_4 32 E0/0
* VSSI_5 60 E28/0

## SYS



* SYS_RST 23 N23/0
* SYS_PLLSELA0 24 N24/0
* SYS_PLLSELA1 25 N25/0
* SYS_PLLCLK 26 N26/0
* SYS_PLLTESTOUT 27 N27/0
* SYS_PLLVCOUT 36 E4/0

## MTWI

I2C.


* MTWI_SDA 90 S26/0
* MTWI_SCL 91 S27/0

## MSPI0

* MSPI0_CK 37 E5/0
* MSPI0_NSS 38 E6/0
* MSPI0_MOSI 39 E7/0
* MSPI0_MISO 40 E8/0

## SDR



* SDR_DQM0 68 S4/0
* SDR_D0 69 S5/0
* SDR_D1 70 S6/0
* SDR_D2 71 S7/0
* SDR_D3 72 S8/0
* SDR_D4 73 S9/0
* SDR_D5 74 S10/0
* SDR_D6 75 S11/0
* SDR_D7 76 S12/0
* SDR_AD0 77 S13/0
* SDR_AD1 78 S14/0
* SDR_AD2 79 S15/0
* SDR_AD3 80 S16/0
* SDR_AD4 81 S17/0
* SDR_AD5 82 S18/0
* SDR_AD6 83 S19/0
* SDR_AD7 84 S20/0
* SDR_AD8 85 S21/0
* SDR_AD9 86 S22/0
* SDR_BA0 87 S23/0
* SDR_BA1 88 S24/0
* SDR_AD10 100 W4/0
* SDR_AD11 101 W5/0
* SDR_AD12 102 W6/0
* SDR_DQM1 103 W7/0
* SDR_D8 104 W8/0
* SDR_D9 105 W9/0
* SDR_D10 106 W10/0
* SDR_D11 107 W11/0
* SDR_D12 108 W12/0
* SDR_D13 109 W13/0
* SDR_D14 110 W14/0
* SDR_D15 111 W15/0
* SDR_CLK 112 W16/0
* SDR_CKE 113 W17/0
* SDR_RASn 114 W18/0
* SDR_CASn 115 W19/0
* SDR_WEn 116 W20/0
* SDR_CSn0 117 W21/0

## Unused Pinouts (spare as GPIO) for 'Libre-SOC 180nm'

| Pin | Mux0        | Mux1        | Mux2        | Mux3        |
| --- | ----------- | ----------- | ----------- | ----------- |
|  30 | N VSSI_7    |             |             |             |
|  31 | N VDDI_7    |             |             |             |
|  34 | E VDDI_4    |             |             |             |
|  35 | E VSSI_4    |             |             |             |
|  62 | E VSSI_5    |             |             |             |
|  63 | E VDDI_5    |             |             |             |
|  64 | S VDDE_0    |             |             |             |
|  65 | S VSSE_0    |             |             |             |
|  66 | S VDDI_0    |             |             |             |
|  67 | S VSSI_0    |             |             |             |
|  92 | S VSSI_1    |             |             |             |
|  93 | S VDDI_1    |             |             |             |
|  94 | S VSSE_1    |             |             |             |
|  95 | S VDDE_1    |             |             |             |
|  96 | W VDDE_2    |             |             |             |
|  97 | W VSSE_2    |             |             |             |
|  98 | W VDDI_2    |             |             |             |
|  99 | W VSSI_2    |             |             |             |
| 124 | W VSSI_3    |             |             |             |
| 125 | W VDDI_3    |             |             |             |
| 126 | W VSSE_3    |             |             |             |
| 127 | W VDDE_3    |             |             |             |

# Reference Datasheets

datasheets and pinout links

* <http://datasheets.chipdb.org/AMD/8018x/80186/amd-80186.pdf>
* <http://hands.com/~lkcl/eoma/shenzen/frida/FRD144A2701.pdf>
* <http://pinouts.ru/Memory/sdcard_pinout.shtml>
* p8 <http://www.onfi.org/~/media/onfi/specs/onfi_2_0_gold.pdf?la=en>
* <https://www.heyrick.co.uk/blog/files/datasheets/dm9000aep.pdf>
* <http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4393.pdf>
* <https://www.nxp.com/docs/en/data-sheet/MCF54418.pdf>
* ULPI OTG PHY, ST <http://www.st.com/en/interfaces-and-transceivers/stulpi01a.html>
* ULPI OTG PHY, TI TUSB1210 <http://ti.com/product/TUSB1210/>

# Pin Bank starting points and lengths

* E 32 32 2
* N 0 32 2
* S 64 32 2
* W 96 32 2