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Luke Kenneth Casson Leighton schreef op wo 25-03-2020 om 15:53 [+0000]:
> On Wed, Mar 25, 2020 at 1:46 PM Staf Verhaegen <staf@fibraservi.eu> wrote=
:
> a workaround (fallback position) is, we use DFF latches.  i created a"byp=
ass latch" function which creates DFF latches with such acombinatorial bypa=
ss: we actually use them quite a lot (includingbetween pipeline stages so t=
hat we can programmatically cut the numberof pipeline stages in half at the=
 flick of a switch).

Would like to make separate side remark here. In ASICs MUXes are relative e=
xpensive gates with respect to delay and power. So if this principle is gen=
erally applied over the whole design it will make it difficult to make a ch=
ip that is competitive in power/performance compared to ARM/x86 CPUs.
In general if you are trying to optimize power/performance of your chip the=
 KISS (keep it simple stupid) is your friend. In that respect your complex =
dual ISA decoder will have a power cost.

greets,
Staf.



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