# Dynamic Partitioned Slice (`SimdSlice`)
In order to match the semantics of nmigen's `Slice` class, `SimdSlice` has to have each element of the result have
exactly the same `Shape` as the result of slicing the input `SimdSignal`'s corresponding element.
## Example code:
```python
a_s = SimdSignal(...)
a = a_s.sig # shorthand to make table smaller
b_s = a_s[3:6]
b = b_s.sig # shorthand to make table smaller
```
## `a`'s Elements:
Bit # |
63…56 |
55…48 |
47…40 |
39…32 |
31…24 |
23…16 |
15…8 |
7…0 |
ElWid: 8-bit |
a[56:64] |
a[48:56] |
a[40:48] |
a[32:40] |
a[24:32] |
a[16:24] |
a[8:16] |
a[0:8] |
ElWid: 16-bit |
a[48:64] |
a[32:48] |
a[16:32] |
a[0:16] |
ElWid: 32-bit |
a[32:64] |
a[0:32] |
ElWid: 64-bit |
a[0:64] |
So, slicing bits `3:6` of a 32-bit element of `a` must, because we have to match nmigen, produce a 3-bit element, which might seem like no problem, however, slicing bits `3:6` of a 16-bit element of a 64-bit `SimdSignal` must *also* produce a 3-bit element, so, in order to get a `SimdSignal` where *all* elements are 3-bit elements, as required by `SimdSlice`'s output, we have to introduce padding:
## `b`'s Elements:
Bit # |
23…21 |
20…18 |
17…15 |
14…12 |
11…9 |
8…6 |
5…3 |
2…0 |
ElWid: 8-bit |
b[21:24] |
b[18:21] |
b[15:18] |
b[12:15] |
b[9:12] |
b[6:9] |
b[3:6] |
b[0:3] |
ElWid: 16-bit |
Padding |
b[18:21] |
Padding |
b[12:15] |
Padding |
b[6:9] |
Padding |
b[0:3] |
ElWid: 32-bit |
Padding |
b[12:15] |
Padding |
b[0:3] |
ElWid: 64-bit |
Padding |
b[0:3] |
# Partitioned SIMD Design implications
Slice is the very first of the entire suite of sub-modules of Partitioned
SimdSignal that requires (and propagates) fixed element widths. All other
sub-modules have up until this point been a fixed *overall* width where the
element widths adapt to completely fill the entire underlying Signal.
Given that this new width context is then passed through to other SimdSignals,
the entire SimdSignal suite has to adapt to this change in requirements.
It is however not as big an adaptation as it first seems.