# High-level architectural Requirements * SMP Cache coherency (TileLink?) * Minumum 800mhz * Minimum 2-core SMP, more likely 4-core uniform design, each core with full 4-wide SIMD-style predicated ALUs * 6GFLOPS single-precision FP * 128 64-bit FP and 128 64-bit INT register files * RV64GC compliance for running full GNU/Linux-based OS * SimpleV compliance * xBitManip (required for VPU and ideal for predication) * 4-lane 2Rx1W SRAMs for registers numbered 32 and above; Multi-R x Multi-W for registers 1-31. TODO: consider 2R for registers to be used as predication targets if >= 32. * Idea: generic implementation of ports on register file so as to be able to experiment with different arrangements. * Potentially: Lane-swapping / crossing / data-multiplexing bus on register data (particularly because of SHAPE-REMAP (1D/2D/3D) * Potentially: Registers subdivided into 16-bit, to match elwidth down to 16-bit (for FP16). 8-bit elwidth only goes down as far as twin-SIMD (with predication). This requires registers to have extra hidden bits: register x30 is now "x30:0+x30.1+x30.2+x30.3". have to discuss. # Conversation Notes ---- 'm thinking about using tilelink (or something similar) internally as having a cache-coherent protocol is required for implementing Vulkan (unless you want to turn off the cache for the GPU memory, which I don't think is a good idea), axi is not a cache-coherent protocol, and tilelink already has atomic rmw operations built into the protocol. We can use an axi to tilelink bridge to interface with the memory. I'm thinking we will want to have a dual-core GPU since a single core with 4xSIMD is too slow to achieve 6GFLOPS with a reasonable clock speed. Additionally, that allows us to use an 800MHz core clock instead of the 1.6GHz we would otherwise need, allowing us to lower the core voltage and save power, since the power used is proportional to F\*V^2. (just guessing on clock speeds.) ---- I don't know about power, however I have done some research and a 4Kbyte (or 16, icr) SRAM (what I was thinking of for a tile buffer) takes in the ballpark of 1000 um^2 in 28nm. Using a 4xFMA with a banked register file where the bank is selected by the lower order register number means we could probably get away with 1Rx1W SRAM as the backing memory for the register file, similarly to Hwacha. I would suggest 8 banks allowing us to do more in parallel since we could run other units in parallel with a 4xFMA. 8 banks would also allow us to clock gate the SRAM banks that are not in use for the current clock cycle allowing us to save more power. Note that the 4xFMA could be 4 separately allocated FMA units, it doesn't have to be SIMD style. If we have enough hw parallelism, we can under-volt and under-clock the GPU cores allowing for a more efficient GPU. If we are using the GPU cores as CPU cores as well, I think it would be important to be able to use a faster clock speed when not using the extended registers (similar to how Intel processors use a lower clock rate when AVX512 is in use) so that scalar code is not slowed down too much. > > Using a 4xFMA with a banked register file where the bank is selected by > the > > lower order register number means we could probably get away with 1Rx1W > > SRAM as the backing memory for the register file, similarly to Hwacha. > > okaaay.... sooo... we make an assumption that the top higher "banks" > are pretty much always going to be "vectorised", such that, actually, > they genuinely don't need to be 6R-4W (or whatever). > Yeah pretty much, though I had meant the bank number comes from the least-significant bits of the 7-bit register number. ---- Assuming 64-bit operands: If you could organize 2 SRAM macros and use the pair of them to read/write 4 registers at a time (256-bits). The pipeline will allow you to dedicate 3 cycles for reading and 1 cycle for writing (4 registers each). RS1 = Read of operand S1 WRd = Write of result Dst FMx = Floating Point Multiplier, x = stage. |RS1|RS2|RS3|FWD|FM1|FM2|FM3|FM4| |FWD|FM1|FM2|FM3|FM4| |FWD|FM1|FM2|FM3|FM4| |FWD|FM1|FM2|FM3|FM4|WRd| |RS1|RS2|RS3|FWD|FM1|FM2|FM3|FM4| |FWD|FM1|FM2|FM3|FM4| |FWD|FM1|FM2|FM3|FM4| |FWD|FM1|FM2|FM3|FM4|WRd| |RS1|RS2|RS3|FWD|FM1|FM2|FM3|FM4| |FWD|FM1|FM2|FM3|FM4| |FWD|FM1|FM2|FM3|FM4| |FWD|FM1|FM2|FM3|FM4|WRd| The only trick is getting the read and write dedicated on different clocks. When the RS3 operand is not needed (60% of the time) you can use the time slot for reading or writing on behalf of memory refs; STs read, LDs write. You will find doing VRFs a lot more compact this way. In GPU land we called the flip-flops orchestrating the timing "collectors". # References * * * Register File Bank Cacheing * Discussion *