# Roadmap

Under development

* check with the RISC-V LLVM backend maintainer and
  * if they aren't going to complete the RV64GC codegen support soon,
  * start working on adding support for RV64GC codegen based on
    <https://github.com/lowRISC/riscv-llvm> using
    https://github.com/andestech/riscv-llvm/tree/riscv-release_50/lib/Target/RISCV
    for reference.
* Add support for RV64GC on Linux to Rust in order to write the user-space
  graphics driver in Rust, I can start by using andestech/riscv-llvm if
  not implementing RV64GC for LLVM
* Implement Simple-V support in Spike
* Add Linux support for Simple-V & Asymmetric Multi Processing
* Implement Simple-V support in LLVM & wire up Rust's SIMD to support it
* Start working on the HW design & figure out the remainder of the plan