Return-path: Envelope-to: publicinbox@libre-riscv.org Delivery-date: Fri, 27 Mar 2020 09:40:57 +0000 Received: from localhost ([::1] helo=libre-riscv.org) by libre-riscv.org with esmtp (Exim 4.89) (envelope-from ) id 1jHlU0-00037X-Ib; Fri, 27 Mar 2020 09:40:56 +0000 Received: from vps2.stafverhaegen.be ([85.10.201.15]) by libre-riscv.org with esmtp (Exim 4.89) (envelope-from ) id 1jHlTy-00037R-Vo for libre-riscv-dev@lists.libre-riscv.org; Fri, 27 Mar 2020 09:40:55 +0000 Received: from hpdc7800 (hpdc7800 [10.0.0.1]) by vps2.stafverhaegen.be (Postfix) with ESMTP id B5E5311C05D7 for ; Fri, 27 Mar 2020 10:40:54 +0100 (CET) Message-ID: From: Staf Verhaegen To: libre-riscv-dev@lists.libre-riscv.org Date: Fri, 27 Mar 2020 10:40:50 +0100 In-Reply-To: References: <29b1a9ecedda151dc9c8da6516c3691dfede62ef.camel@fibraservi.eu> <6fa40cb78b3f8c013ca4953ccb4daa5c23e3b501.camel@fibraservi.eu> <7b5a312befec67dbf14d31f5bb4c418c8784e787.camel@fibraservi.eu> <65e762e270e3660044604cc48f4fbd554d34af13.camel@fibraservi.eu> Organization: FibraServi bvba X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) Mime-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: Re: [libre-riscv-dev] cache SRAM organisation X-BeenThere: libre-riscv-dev@lists.libre-riscv.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Libre-RISCV General Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Libre-RISCV General Development Content-Type: multipart/mixed; boundary="===============1910170872914261038==" Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org Sender: "libre-riscv-dev" --===============1910170872914261038== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-J95ryvYZyzhS5ctacdhx" --=-J95ryvYZyzhS5ctacdhx Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Luke Kenneth Casson Leighton schreef op vr 27-03-2020 om 09:16 [+0000]: > On Fri, Mar 27, 2020 at 9:09 AM Staf Verhaegen wrote= : > > I still feel you intermix synchronous and write-through in this stateme= nt, the above seems to be possible with synchronous SRAMs. >=20 > this would be good. what would help clarify immensely is if you couldlet= us know what options to nmigen Memory class are "supported".then it is rea= lly clear. The nmigen Memory abstraction does not seem to allow a good representation = of a write-through SRAM. AFAICS it does not allow to have the output of the= read port be changed by what you write on the write port. greets, Staf. --=-J95ryvYZyzhS5ctacdhx-- --===============1910170872914261038== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj di1kZXYK --===============1910170872914261038==--