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Date: Fri, 01 May 2020 23:21:10 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
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X-Bugzilla-Product: Libre-SOC's first SoC
X-Bugzilla-Component: Source Code
X-Bugzilla-Version: unspecified
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X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: lkcl@lkcl.net
X-Bugzilla-Status: CONFIRMED
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Message-ID: <bug-298-13-FXFDvTi3x6@https.bugs.libre-soc.org/>
In-Reply-To: <bug-298-13@https.bugs.libre-soc.org/>
References: <bug-298-13@https.bugs.libre-soc.org/>
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Subject: [libre-riscv-dev] [Bug 298] consider using sum-addressed decoder in
 L1 cache (maybe also L1 I cache)
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