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Date: Sat, 28 Mar 2020 14:34:31 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
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X-Bugzilla-Product: Libre-SOC's first SoC
X-Bugzilla-Component: Source Code
X-Bugzilla-Version: unspecified
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X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: lkcl@lkcl.net
X-Bugzilla-Status: CONFIRMED
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Message-ID: <bug-270-13-UNec52UIvg@http.bugs.libre-riscv.org/>
In-Reply-To: <bug-270-13@http.bugs.libre-riscv.org/>
References: <bug-270-13@http.bugs.libre-riscv.org/>
X-Bugzilla-URL: http://bugs.libre-riscv.org/
Auto-Submitted: auto-generated
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Subject: [libre-riscv-dev] [Bug 270] investigate nmigen clock gating
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