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Date: Tue, 24 Mar 2020 14:24:22 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
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X-Bugzilla-Product: Libre-SOC's first SoC
X-Bugzilla-Component: Source Code
X-Bugzilla-Version: unspecified
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X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: lkcl@lkcl.net
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Message-ID: <bug-72-13-wAMUuiO20O@http.bugs.libre-riscv.org/>
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Auto-Submitted: auto-generated
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Subject: [libre-riscv-dev] [Bug 72] verilog to nmigen converter (full or
 partial) needed
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