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Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 13:46 [+0100]:
> On Fri, May 8, 2020 at 1:44 PM Yehowshua <yimmanuel3@gatech.edu> wrote:
> > I talked to Raptor and if Series A doesn=E2=80=99t pan out in August, R=
aptor is willing to foot 30k for PLL design in exchange for some equity.
>=20
> that's fantastic.  it would give us (and any other team)Foundry-independe=
nce.  normally the PLL is available as a StandardCell from a Foundry... but=
 only under NDA.

Be aware that PLL is an analog block meaning that if you let it design for =
a certain process from a certain foundry it will only work for that node an=
d foundry. It is not portable like RTL code is unless specifically designed=
 for that but analog designers typically don't know how to do that. Also in=
 order to design the PLL you need NDA to access the PDK which likely also f=
orbids making the final GDSII of your design public.

Also giving away equity gives cause for other type of dependence...

greets,
Staf.



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