# Build instructions for Microwatt TODO WIP integrate from useful links: * * * prerequisite tools: * install verilator: * install yosys * install ghdl-yosys-plugin After installing ghdl-yosys-plugin use schroot to switch environment schroot -c bullseye_ghdl git clone https://git.libre-soc.org/git/microwatt.git git checkout -b verilator_trace export FPGA_TARGET=verilator make microwatt-verilator Then run the resulting binary time ./microwatt-verilator If everything works correcly it will print out an light bulb in ascii art with the message Microwatt, it works. On my ASUS KGPE D16 this takes real 1m4.986s user 1m4.373s sys 0m0.013s ## Building the kernel On a POWER9 there is no need to install gcc-powerpc64le-linux-gnu, you can omit CROSS_COMPILE and ARCH in this case apt install gcc-powerpc64le-linux-gnu apt install flex bison lz4 git clone -b microwatt-5.7 https://git.kernel.org/pub/scm/linux/kernel/git/joel/microwatt.git cd microwatt wget https://ftp.libre-soc.org/microwatt-linux-5.7.patch patch -p1 < microwatt-linux-5.7.patch wget https://ftp.libre-soc.org/rootfs.cpio CROSS_COMPILE="ccache powerpc64le-linux-gnu-" ARCH=powerpc make -j8 O=microwatt microwatt_defconfig CROSS_COMPILE="ccache powerpc64le-linux-gnu-" ARCH=powerpc make -j8 O=microwatt This will produce a file microwatt/arch/powerpc/boot/dtbImage.microwatt ## Building sdram_init.bin This needs gcc-powerpc64le-linux-gnu if cross compilation is used. cd microwatt cd litedram/gen-src/sdram_init/ make ## Building microwatt-verilator using the libre-soc core cd /path/to/soc make microwatt_external_core cp external_core_top.v /path/to/microwatt cd /path/to/microwatt export FPGA_TARGET=verilator export GHDLSYNTH=ghdl make microwatt-verilator ## Running the simulation cp microwatt/arch/powerpc/boot/dtbImage.microwatt ./microwatt-verilator sdram_init.bin dtbImage.microwatt ## Building the bitstring for OrangeCrab cd microwatt export FPGA_TARGET=ORANGE-CRAB export GHDLSYNTH=ghdl make microwatt.bit ## flashing the bitstring to the OrangeCrab make prog # this will run OpenOCD ## TODO: buildroot * https://github.com/shenki/buildroot/commits/microwatt * https://codeconstruct.com.au/docs/microwatt-orangecrab/ # Notes for ulx3s notes for how to compile for ulx3s git clone https://github.com/kost/fujprog (follow build procedure shown in fujprog README) git clone https://git.libre-soc.org/git/microwatt.git git checkout -b verilator_trace export FPGA_TARGET=ulx3s make microwatt.svf fujprog microwatt.svf # Notes for nextpnr-xilinx superceded: see page [[nextpnr-xilinx]] and devscript for compiling nextpnr-xilinx and making it useable for nmigen to compile for the digilent arty-a7-100t, requires a little futzing around, using the symbiflow version of prjxray-db instead of the one recommended as a submodule git clone https://github.com/gatecat/nextpnr-xilinx cd nextpnr-xilinx git checkout cd8b15db6ff5c1a7f10a9e git submodule init git submodule update cd xilinx/external mv prjxray-db prjxray-db-no git clone https://github.com/SymbiFlow/prjxray-db cd prjxray-db git checkout 0a0addedd73e7 cp ./artix7/xc7a100t/*.json \ ./artix7/xc7a100tcsg324-1 cd ../../.. cmake -DARCH=xilinx . make make install python3 xilinx/python/bbaexport.py --device xc7a100tcsg324-1 --bba xilinx/xc7a100t.bba ./bbasm --l xilinx/xc7a100t.bba xilinx/xc7a100t.bin mkdir -p /usr/share/nextpnr/xilinx-chipdb cp xilinx/*.bin /usr/share/nextpnr/xilinx-chipdb cp -aux xilinx/external/prjxray-db /usr/share/nextpnr # Additional Useful Info for UART <-> USB Serial Interface Through OrangeCrab's Built-in USB Interface This uses OrangeCrab's built-in USB interface, rather than needing a separate USB-serial adapter. see the following for further details: * * # running orangecrab-examples before flashing microwatt See If the OrangeCrab is running in DFU mode, lsusb will show: 1209:5af0 Generic OrangeCrab r0.2 DFU Bootloader v3.1-6-g62e92e2 OrangeCrab has two DFU devices: Found DFU: [1209:5af0] ver=0101, devnum=22, cfg=1, intf=0, path="1-4.2", alt=1, name="0x00100000 RISC-V Firmware", serial="UNKNOWN" Found DFU: [1209:5af0] ver=0101, devnum=22, cfg=1, intf=0, path="1-4.2", alt=0, name="0x00080000 Bitstream", serial="UNKNOWN" Then clone and patch orangecrab-examples: git clone https://github.com/orangecrab-fpga/orangecrab-examples patch -p1 < orangecrab-examples.diff To build and flash the example: pushd orangecrab-examples/nmigen python3 blink.py popd sudo dfu-util -D orangecrab-examples/nmigen/build/top.bit -a 0