Return-path: Envelope-to: publicinbox@libre-riscv.org Delivery-date: Sat, 09 May 2020 10:12:49 +0100 Received: from localhost ([::1] helo=libre-riscv.org) by libre-soc.org with esmtp (Exim 4.89) (envelope-from ) id 1jXLXM-0005eI-MO; Sat, 09 May 2020 10:12:48 +0100 Received: from vps2.stafverhaegen.be ([85.10.201.15]) by libre-soc.org with esmtp (Exim 4.89) (envelope-from ) id 1jXLXK-0005eC-RZ for libre-riscv-dev@lists.libre-riscv.org; Sat, 09 May 2020 10:12:46 +0100 Received: from hpdc7800 (hpdc7800 [10.0.0.1]) by vps2.stafverhaegen.be (Postfix) with ESMTP id 0BEDB11C04F6 for ; Sat, 9 May 2020 11:12:46 +0200 (CEST) Message-ID: <792ac37b0c72350337f07c758d51a24eaa9ac532.camel@fibraservi.eu> From: Staf Verhaegen To: libre-riscv-dev@lists.libre-riscv.org Date: Sat, 09 May 2020 11:12:40 +0200 In-Reply-To: <3BD26F5C-BB6D-4011-89E6-EC06215DEDEA@gatech.edu> References: <3BD26F5C-BB6D-4011-89E6-EC06215DEDEA@gatech.edu> Organization: FibraServi bvba X-Mailer: Evolution 3.28.5 (3.28.5-8.el7) Mime-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: Re: [libre-riscv-dev] Pinout, interfaces, Rudi, and Raptor X-BeenThere: libre-riscv-dev@lists.libre-riscv.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Libre-RISCV General Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Libre-RISCV General Development Content-Type: multipart/mixed; boundary="===============1441781585780467197==" Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org Sender: "libre-riscv-dev" --===============1441781585780467197== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-q7g7wYzd/YlocVdASqQr" --=-q7g7wYzd/YlocVdASqQr Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Yehowshua schreef op vr 08-05-2020 om 10:20 [-0400]: > Hello Luke, So I see we have some pinout sdefine here. > https://libre-soc.org/shakti/m_class/pinouts/ >=20 > My suggestion is to drop the pinmux for now. We should probably update th= at page(or create a similar page) to reflect what we=E2=80=99re targeting f= or October. > IIRC, we=E2=80=99re targeting QFP. I don=E2=80=99t see the dimensions or = form factor we=E2=80=99re targeting listed there however. We should talk ab= out that. > Also, talked with Tim and SDR could work for the first SBC. LiteX also su= pports SDR which is good for us as it doesn=E2=80=99t require a PHY like DD= R making it simpler. You refer to a first SBC preferably low-cost. The October prototype tape-ou= t will not be cost-effective for that. It is a multi-project wafer. You can= order extra wafers but it does mean that the cost of that wafer is divided= over much less devices; meaning the cost will be around $32 per chip and s= ome of them will not be functional; in microelectrics you never have 100% y= ield. Also I think there is limit on only be able to get at most 1000 chips= this way. If you want lower cost per unit you need to go for a full mask with a so-ca= lled engineering lot of 12 wafers. This will have a high startup cost. A fi= rst crude estimation is between $70000 and $75000. This give a few thousand= of chips; exact number depends on the size of the chip. An extra engineeri= ng lot of 12 wafers will be around $18000. For this it means you will need to a new tape-out so you can add extra peri= pherals that were not on the prototype tape-out. greets, Staf. --=-q7g7wYzd/YlocVdASqQr-- --===============1441781585780467197== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj di1kZXYK --===============1441781585780467197==--