Return-path: Envelope-to: publicinbox@libre-riscv.org Delivery-date: Wed, 01 Apr 2020 16:19:20 +0100 Received: from localhost ([::1] helo=libre-riscv.org) by libre-riscv.org with esmtp (Exim 4.89) (envelope-from ) id 1jJf9D-0002re-Rx; Wed, 01 Apr 2020 16:19:19 +0100 Received: from vps2.stafverhaegen.be ([85.10.201.15]) by libre-riscv.org with esmtp (Exim 4.89) (envelope-from ) id 1jJf9C-0002rY-2s for libre-riscv-dev@lists.libre-riscv.org; Wed, 01 Apr 2020 16:19:18 +0100 Received: from hpdc7800 (hpdc7800 [10.0.0.1]) by vps2.stafverhaegen.be (Postfix) with ESMTP id 5573811C0550 for ; Wed, 1 Apr 2020 17:19:17 +0200 (CEST) Message-ID: <9f72940ad53e20b7015c45771177e6dff55ae6ab.camel@fibraservi.eu> From: Staf Verhaegen To: libre-riscv-dev@lists.libre-riscv.org Date: Wed, 01 Apr 2020 17:19:12 +0200 In-Reply-To: References: <20200330095605.53c15f0713bab37f5c7121e2@gmx.com> <20200330103226.4cc14532f22a48719e25ea8f@gmx.com> <0a6fab6c-db49-1d8a-6f9d-e387af92eb75@gmail.com> <3AF0E5F3-86A0-4610-82E4-AD6C5BE0E588@gatech.edu> Organization: FibraServi bvba X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) Mime-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: Re: [libre-riscv-dev] additional ddr3 interfaces X-BeenThere: libre-riscv-dev@lists.libre-riscv.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Libre-RISCV General Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Libre-RISCV General Development Content-Type: multipart/mixed; boundary="===============3363447724956210421==" Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org Sender: "libre-riscv-dev" --===============3363447724956210421== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-ZPe2CQ54LCw9vnZn6mEx" --=-ZPe2CQ54LCw9vnZn6mEx Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Luke Kenneth Casson Leighton schreef op wo 01-04-2020 om 11:10 [+0000]: > On Wed, Apr 1, 2020 at 1:44 AM Jacob Lifshay w= rote: > > that would be nice, however the t2080 appears to have a 64-bit memoryin= terface along with some really high-speed serdes -- both of which will bemo= re difficult to achieve. > > However, if we get the funding required for the open-source custom DDR3= interface, we could potentially put two copies on our SoC, >=20 > each DDR3/4 RAM interface adds around 0.4 watts per 800mhz clock ratewhic= h, due to power being a square law, ramps up 1.6 watts by 1600mhz. Power consumption is linear with frequency and square with voltage (P =3D f= * C * V^2). For overclocking increasing frequency also likely means you need to increas= e voltage so you need to increase power consumption more than linear with f= requency. greets, Staf. --=-ZPe2CQ54LCw9vnZn6mEx-- --===============3363447724956210421== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj di1kZXYK --===============3363447724956210421==--