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\title{The Libre-SOC Hybrid CPU-VPU-GPU}
\author{Luke Kenneth Casson Leighton}


\begin{document}

\frame{
   \begin{center}
    \huge{The Libre-SOC Hybrid CPU-VPU-GPU}\\
    \vspace{32pt}
    \Large{and why Libre/Open is crucial}\\
    \Large{(even in a business context)}\\
    \Large{Practical gotchas for Silicon Transparency}\\
    \vspace{24pt}
    \Large{Silicon Salon 2022}\\
    \vspace{16pt}
    \large{Sponsored by NLnet's PET Programme}\\
    \vspace{6pt}
    \large{\today}
  \end{center}
}


\frame{\frametitle{What is the Libre-SOC Project}

 \begin{itemize}
   \item An entirely Libre Vector-enhanced Power ISA compliant
         CPU with enough legs to tackle Supercomputing-class
         workloads.
        \vspace{6pt}
   \item Working closely with the OpenPOWER Foundation: no
         rogue custom instructions.  Both Long-term stability and
         open-ness is key.
        \vspace{6pt}
   \item Huge reliance on Python OO and Software Engineering as
         applied to HDL. Not just traditional Verification: unit
         tests at every level, Formal Correctness Proofs as unit
         tests. "python3 setup.py test"
        \vspace{6pt}
   \item Using Libre VLSI Tools: coriolis2 (by Sorbonne University)
         ultimate goal is to have the GDS-II Files publicly reproducible
        \vspace{6pt}

  \end{itemize}
}


\frame{\frametitle{What challenges does a Crypto-Wallet ASIC face?}

 \begin{itemize}
   \item Industry-endemic paranoid 5-level-deep NDA Chain.  Foundry NDAs
         themselves are under NDA. Sharing between teams inside the same
         company is prohibited! Cell Libraries: NDA'd. PDKs: NDA'd.
         HDL designs: NDA'd.
        \vspace{6pt}
   \item Power-analysis attacks. Timing attacks. EMF attacks.  Standards
         Verification (FIPS ain't it).  Toolchain attacks.  Cacheing is out:
         performance will suck.
        \vspace{6pt}
   \item Achieving Full Transparency - a critical goal - is almost impossible
         to achieve.  Ultimately, you need to buy (or build) your own Foundry.
        \vspace{6pt}
   \item Production and Development costs (NREs) almost certainly dwarf the
         Sales costs.
        \vspace{6pt}
  \end{itemize}
}


\frame{\frametitle{Pragmatic solutions}

 \begin{itemize}
   \item Use Formal Correctness Proofs at every step. Caveat: proofs are
         only as good as the mathematicians that write them!
        \vspace{1pt}
   \item Work with Standards bodies (e.g. OpenPOWER Foundation ISA WG) and
         Members with similar interests.
         Custom Extension with zero public review == bad.
        \vspace{1pt}
   \item Unstable PLLs to detect rogue EMF
        \vspace{1pt}
   \item Develop a product that has a larger total market (an SoC)
        \vspace{1pt}
   \item Accept that some levels of NDA are "out of reach" for now.
        \vspace{1pt}
   \item Use E-Fabless "ChipIgnite" to at least get the NREs down.
        \vspace{1pt}
   \item Ultimately: buy your own Foundry, make the PDK and Cell Library public.
         Only use Libre VLSI tools (limits to around 130 nm at the moment).
         Everything is "early days" in this space
        \vspace{1pt}
  \end{itemize}
}


\frame{
  \begin{center}
    {\Huge The end\vspace{12pt}\\
		   Thank you\vspace{12pt}\\
		   Questions?\vspace{12pt}
	}
  \end{center}
  
  \begin{itemize}
	\item Discussion: http://lists.libre-soc.org
	\item Libera.Chat IRC \#libre-soc
	\item http://libre-soc.org/
	\item http://nlnet.nl/PET
	\item https://libre-soc.org/nlnet/\#faq
  \end{itemize}
}


\end{document}
