# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-

        LOGICAL_SYNTHESIS = Yosys
       PHYSICAL_SYNTHESIS = Coriolis
               DESIGN_KIT = nsxlib

#           YOSYS_FLATTEN = Yes
                     CORE = fpmul64
            USE_CLOCKTREE = Yes
                USE_DEBUG = No
                 USE_KITE = No

                 NETLISTS = $(shell cat cells.lst)

                VST_FLAGS = --vst-use-concat

 include ./mk/design-flow.mk


blif:      fpmul64.blif
vst:       fpmul64.vst
layout:    fpmul64_cts_r.ap
gds:       fpmul64_cts_r.gds

lvx:       lvx-fpmul64_cts_r
druc:      druc-fpmul64_cts_r
view:      cgt-fpmul64_cts_r