LOGICAL_SYNTHESIS = Yosys
       PHYSICAL_SYNTHESIS = Coriolis
               DESIGN_KIT = sxlib

#            YOSYS_SET_TOP = Yes
                    CHIP  = chip
                    CORE  = ls180
                   MARGIN = 2
                   BOOMOPT =
                   BOOGOPT =
                   LOONOPT =
                   NSL2VHOPT = -vasy # -split -p
            USE_CLOCKTREE = Yes
                USE_DEBUG = No
                 USE_KITE = No
                VST_FLAGS = --vst-use-concat

                 NETLISTS = $(shell cat cells.lst)
#            YOSYS_FLATTEN = $(shell cat flatten.lst)



 include ./mk/design-flow.mk

pinmux:
	python ../pinmux/src/pinmux_generator.py -v -s ls180 -o coriolis2/ls180
	ln -f -s ../pinmux/src/parse.py coriolis2/pinparse.py

blif:      ls180.blif
vst:       ls180.vst

lvx:       lvx-chip_cts_r
druc:      druc-chip_cts_r
dreal:     dreal-chip_cts_r
flatph:     flatph-chip_cts_r
view:      cgt-chip_cts_r

layout:    chip_cts_r.ap
gds:       chip_cts_r.gds
gds_flat:  chip_cts_r_flat.gds
cif:  	   chip_cts_r.cif


view:      cgt-chip_cts_r
sim:       asimut-ls180_cts_r