//-------------------------------------------------------------------------------- // Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-04-18 11:23:13 //-------------------------------------------------------------------------------- module ls180( input wire [15:0] gpio_i, output wire [15:0] gpio_o, output wire [15:0] gpio_oe, input wire eint_0, input wire eint_1, input wire eint_2, output wire [12:0] sdram_a, input wire [15:0] sdram_dq_i, output wire [15:0] sdram_dq_o, output wire [15:0] sdram_dq_oe, output wire sdram_we_n, output wire sdram_ras_n, output wire sdram_cas_n, output wire sdram_cs_n, output wire sdram_cke, output wire [1:0] sdram_ba, output wire [1:0] sdram_dm, output wire sdram_clock, output wire i2c_scl, input wire i2c_sda_i, output wire i2c_sda_o, output wire i2c_sda_oe, output wire spimaster_clk, output wire spimaster_mosi, output wire spimaster_cs_n, input wire spimaster_miso, input wire uart_tx, input wire uart_rx, input wire sys_clk, input wire sys_rst, input wire jtag_tms, input wire jtag_tck, input wire jtag_tdi, output wire jtag_tdo, input wire [39:0] nc ); (* ram_style = "distributed" *) reg libresocsim_reset_storage = 1'd0; reg libresocsim_reset_re = 1'd0; (* ram_style = "distributed" *) reg [31:0] libresocsim_scratch_storage = 32'd305419896; reg libresocsim_scratch_re = 1'd0; wire [31:0] libresocsim_bus_errors_status; wire libresocsim_bus_errors_we; wire libresocsim_reset; wire libresocsim_bus_error; reg [31:0] libresocsim_bus_errors = 32'd0; wire libresocsim_libresoc_reset; reg [15:0] libresocsim_libresoc_interrupt = 16'd0; wire [28:0] libresocsim_libresoc_dbus_adr; wire [63:0] libresocsim_libresoc_dbus_dat_w; wire [63:0] libresocsim_libresoc_dbus_dat_r; wire [7:0] libresocsim_libresoc_dbus_sel; wire libresocsim_libresoc_dbus_cyc; wire libresocsim_libresoc_dbus_stb; reg libresocsim_libresoc_dbus_ack = 1'd0; wire libresocsim_libresoc_dbus_we; reg libresocsim_libresoc_dbus_err = 1'd0; wire [28:0] libresocsim_libresoc_ibus_adr; wire [63:0] libresocsim_libresoc_ibus_dat_w; wire [63:0] libresocsim_libresoc_ibus_dat_r; wire [7:0] libresocsim_libresoc_ibus_sel; wire libresocsim_libresoc_ibus_cyc; wire libresocsim_libresoc_ibus_stb; reg libresocsim_libresoc_ibus_ack = 1'd0; wire libresocsim_libresoc_ibus_we; reg libresocsim_libresoc_ibus_err = 1'd0; wire [29:0] libresocsim_libresoc_xics_icp_adr; wire [31:0] libresocsim_libresoc_xics_icp_dat_w; wire [31:0] libresocsim_libresoc_xics_icp_dat_r; wire [3:0] libresocsim_libresoc_xics_icp_sel; wire libresocsim_libresoc_xics_icp_cyc; wire libresocsim_libresoc_xics_icp_stb; wire libresocsim_libresoc_xics_icp_ack; wire libresocsim_libresoc_xics_icp_we; wire [2:0] libresocsim_libresoc_xics_icp_cti; wire [1:0] libresocsim_libresoc_xics_icp_bte; wire libresocsim_libresoc_xics_icp_err; wire [29:0] libresocsim_libresoc_xics_ics_adr; wire [31:0] libresocsim_libresoc_xics_ics_dat_w; wire [31:0] libresocsim_libresoc_xics_ics_dat_r; wire [3:0] libresocsim_libresoc_xics_ics_sel; wire libresocsim_libresoc_xics_ics_cyc; wire libresocsim_libresoc_xics_ics_stb; wire libresocsim_libresoc_xics_ics_ack; wire libresocsim_libresoc_xics_ics_we; wire [2:0] libresocsim_libresoc_xics_ics_cti; wire [1:0] libresocsim_libresoc_xics_ics_bte; wire libresocsim_libresoc_xics_ics_err; wire [29:0] libresocsim_libresoc_jtag_wb_adr; wire [31:0] libresocsim_libresoc_jtag_wb_dat_w; wire [31:0] libresocsim_libresoc_jtag_wb_dat_r; wire [3:0] libresocsim_libresoc_jtag_wb_sel; wire libresocsim_libresoc_jtag_wb_cyc; wire libresocsim_libresoc_jtag_wb_stb; wire libresocsim_libresoc_jtag_wb_ack; wire libresocsim_libresoc_jtag_wb_we; reg [2:0] libresocsim_libresoc_jtag_wb_cti = 3'd0; reg [1:0] libresocsim_libresoc_jtag_wb_bte = 2'd0; wire libresocsim_libresoc_jtag_wb_err; wire libresocsim_libresoc_jtag_tck; wire libresocsim_libresoc_jtag_tms; wire libresocsim_libresoc_jtag_tdi; wire libresocsim_libresoc_jtag_tdo; reg [63:0] libresocsim_libresoc0 = 64'd0; wire libresocsim_libresoc1; wire libresocsim_libresoc2; wire [63:0] libresocsim_libresoc3; wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; wire libresocsim_libresoc_constraintmanager_eint_0; wire libresocsim_libresoc_constraintmanager_eint_1; wire libresocsim_libresoc_constraintmanager_eint_2; reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i; reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_oe = 16'd0; reg libresocsim_libresoc_constraintmanager_sdram_we_n = 1'd0; reg libresocsim_libresoc_constraintmanager_sdram_ras_n = 1'd0; reg libresocsim_libresoc_constraintmanager_sdram_cas_n = 1'd0; reg libresocsim_libresoc_constraintmanager_sdram_cs_n = 1'd0; reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; wire libresocsim_libresoc_constraintmanager_i2c_scl; wire libresocsim_libresoc_constraintmanager_i2c_sda_i; wire libresocsim_libresoc_constraintmanager_i2c_sda_o; wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; wire libresocsim_libresoc_constraintmanager_spimaster_miso; reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] libresocsim_interface0_converted_interface_dat_r; reg [3:0] libresocsim_interface0_converted_interface_sel = 4'd0; reg libresocsim_interface0_converted_interface_cyc = 1'd0; reg libresocsim_interface0_converted_interface_stb = 1'd0; wire libresocsim_interface0_converted_interface_ack; reg libresocsim_interface0_converted_interface_we = 1'd0; reg [2:0] libresocsim_interface0_converted_interface_cti = 3'd0; reg [1:0] libresocsim_interface0_converted_interface_bte = 2'd0; wire libresocsim_interface0_converted_interface_err; reg libresocsim_converter0_skip = 1'd0; reg libresocsim_converter0_counter = 1'd0; wire libresocsim_converter0_reset; reg [63:0] libresocsim_converter0_dat_r = 64'd0; reg [29:0] libresocsim_interface1_converted_interface_adr = 30'd0; reg [31:0] libresocsim_interface1_converted_interface_dat_w = 32'd0; wire [31:0] libresocsim_interface1_converted_interface_dat_r; reg [3:0] libresocsim_interface1_converted_interface_sel = 4'd0; reg libresocsim_interface1_converted_interface_cyc = 1'd0; reg libresocsim_interface1_converted_interface_stb = 1'd0; wire libresocsim_interface1_converted_interface_ack; reg libresocsim_interface1_converted_interface_we = 1'd0; reg [2:0] libresocsim_interface1_converted_interface_cti = 3'd0; reg [1:0] libresocsim_interface1_converted_interface_bte = 2'd0; wire libresocsim_interface1_converted_interface_err; reg libresocsim_converter1_skip = 1'd0; reg libresocsim_converter1_counter = 1'd0; wire libresocsim_converter1_reset; reg [63:0] libresocsim_converter1_dat_r = 64'd0; wire [29:0] libresocsim_ram_bus_adr; wire [31:0] libresocsim_ram_bus_dat_w; wire [31:0] libresocsim_ram_bus_dat_r; wire [3:0] libresocsim_ram_bus_sel; wire libresocsim_ram_bus_cyc; wire libresocsim_ram_bus_stb; reg libresocsim_ram_bus_ack = 1'd0; wire libresocsim_ram_bus_we; wire [2:0] libresocsim_ram_bus_cti; wire [1:0] libresocsim_ram_bus_bte; reg libresocsim_ram_bus_err = 1'd0; wire [6:0] libresocsim_adr; wire [31:0] libresocsim_dat_r; reg [3:0] libresocsim_we = 4'd0; wire [31:0] libresocsim_dat_w; (* ram_style = "distributed" *) reg [31:0] libresocsim_load_storage = 32'd0; reg libresocsim_load_re = 1'd0; (* ram_style = "distributed" *) reg [31:0] libresocsim_reload_storage = 32'd0; reg libresocsim_reload_re = 1'd0; (* ram_style = "distributed" *) reg libresocsim_en_storage = 1'd0; reg libresocsim_en_re = 1'd0; (* ram_style = "distributed" *) reg libresocsim_update_value_storage = 1'd0; reg libresocsim_update_value_re = 1'd0; reg [31:0] libresocsim_value_status = 32'd0; wire libresocsim_value_we; wire libresocsim_irq; wire libresocsim_zero_status; reg libresocsim_zero_pending = 1'd0; wire libresocsim_zero_trigger; reg libresocsim_zero_clear = 1'd0; reg libresocsim_zero_old_trigger = 1'd0; wire libresocsim_eventmanager_status_re; wire libresocsim_eventmanager_status_r; wire libresocsim_eventmanager_status_we; wire libresocsim_eventmanager_status_w; wire libresocsim_eventmanager_pending_re; wire libresocsim_eventmanager_pending_r; wire libresocsim_eventmanager_pending_we; wire libresocsim_eventmanager_pending_w; (* ram_style = "distributed" *) reg libresocsim_eventmanager_storage = 1'd0; reg libresocsim_eventmanager_re = 1'd0; reg [31:0] libresocsim_value = 32'd0; wire [29:0] ram_bus_ram_bus_adr; wire [31:0] ram_bus_ram_bus_dat_w; wire [31:0] ram_bus_ram_bus_dat_r; wire [3:0] ram_bus_ram_bus_sel; wire ram_bus_ram_bus_cyc; wire ram_bus_ram_bus_stb; reg ram_bus_ram_bus_ack = 1'd0; wire ram_bus_ram_bus_we; wire [2:0] ram_bus_ram_bus_cti; wire [1:0] ram_bus_ram_bus_bte; reg ram_bus_ram_bus_err = 1'd0; wire [4:0] ram_adr; wire [31:0] ram_dat_r; reg [3:0] ram_we = 4'd0; wire [31:0] ram_dat_w; wire sys_clk_1; wire sys_rst_1; wire por_clk; reg int_rst = 1'd1; wire [12:0] dfi_p0_address; wire [1:0] dfi_p0_bank; wire dfi_p0_cas_n; wire dfi_p0_cs_n; wire dfi_p0_ras_n; wire dfi_p0_we_n; wire dfi_p0_cke; wire dfi_p0_odt; wire dfi_p0_reset_n; wire dfi_p0_act_n; wire [15:0] dfi_p0_wrdata; wire dfi_p0_wrdata_en; wire [1:0] dfi_p0_wrdata_mask; wire dfi_p0_rddata_en; reg [15:0] dfi_p0_rddata = 16'd0; reg dfi_p0_rddata_valid = 1'd0; reg [2:0] rddata_en = 3'd0; wire [12:0] sdram_inti_p0_address; wire [1:0] sdram_inti_p0_bank; reg sdram_inti_p0_cas_n = 1'd1; reg sdram_inti_p0_cs_n = 1'd1; reg sdram_inti_p0_ras_n = 1'd1; reg sdram_inti_p0_we_n = 1'd1; wire sdram_inti_p0_cke; wire sdram_inti_p0_odt; wire sdram_inti_p0_reset_n; reg sdram_inti_p0_act_n = 1'd1; wire [15:0] sdram_inti_p0_wrdata; wire sdram_inti_p0_wrdata_en; wire [1:0] sdram_inti_p0_wrdata_mask; wire sdram_inti_p0_rddata_en; reg [15:0] sdram_inti_p0_rddata = 16'd0; reg sdram_inti_p0_rddata_valid = 1'd0; wire [12:0] sdram_slave_p0_address; wire [1:0] sdram_slave_p0_bank; wire sdram_slave_p0_cas_n; wire sdram_slave_p0_cs_n; wire sdram_slave_p0_ras_n; wire sdram_slave_p0_we_n; wire sdram_slave_p0_cke; wire sdram_slave_p0_odt; wire sdram_slave_p0_reset_n; wire sdram_slave_p0_act_n; wire [15:0] sdram_slave_p0_wrdata; wire sdram_slave_p0_wrdata_en; wire [1:0] sdram_slave_p0_wrdata_mask; wire sdram_slave_p0_rddata_en; reg [15:0] sdram_slave_p0_rddata = 16'd0; reg sdram_slave_p0_rddata_valid = 1'd0; reg [12:0] sdram_master_p0_address = 13'd0; reg [1:0] sdram_master_p0_bank = 2'd0; reg sdram_master_p0_cas_n = 1'd1; reg sdram_master_p0_cs_n = 1'd1; reg sdram_master_p0_ras_n = 1'd1; reg sdram_master_p0_we_n = 1'd1; reg sdram_master_p0_cke = 1'd0; reg sdram_master_p0_odt = 1'd0; reg sdram_master_p0_reset_n = 1'd0; reg sdram_master_p0_act_n = 1'd1; reg [15:0] sdram_master_p0_wrdata = 16'd0; reg sdram_master_p0_wrdata_en = 1'd0; reg [1:0] sdram_master_p0_wrdata_mask = 2'd0; reg sdram_master_p0_rddata_en = 1'd0; wire [15:0] sdram_master_p0_rddata; wire sdram_master_p0_rddata_valid; wire sdram_sel; wire sdram_cke_1; wire sdram_odt; wire sdram_reset_n; (* ram_style = "distributed" *) reg [3:0] sdram_storage = 4'd1; reg sdram_re = 1'd0; (* ram_style = "distributed" *) reg [5:0] sdram_command_storage = 6'd0; reg sdram_command_re = 1'd0; wire sdram_command_issue_re; wire sdram_command_issue_r; wire sdram_command_issue_we; reg sdram_command_issue_w = 1'd0; (* ram_style = "distributed" *) reg [12:0] sdram_address_storage = 13'd0; reg sdram_address_re = 1'd0; (* ram_style = "distributed" *) reg [1:0] sdram_baddress_storage = 2'd0; reg sdram_baddress_re = 1'd0; (* ram_style = "distributed" *) reg [15:0] sdram_wrdata_storage = 16'd0; reg sdram_wrdata_re = 1'd0; reg [15:0] sdram_status = 16'd0; wire sdram_we; wire sdram_interface_bank0_valid; wire sdram_interface_bank0_ready; wire sdram_interface_bank0_we; wire [21:0] sdram_interface_bank0_addr; wire sdram_interface_bank0_lock; wire sdram_interface_bank0_wdata_ready; wire sdram_interface_bank0_rdata_valid; wire sdram_interface_bank1_valid; wire sdram_interface_bank1_ready; wire sdram_interface_bank1_we; wire [21:0] sdram_interface_bank1_addr; wire sdram_interface_bank1_lock; wire sdram_interface_bank1_wdata_ready; wire sdram_interface_bank1_rdata_valid; wire sdram_interface_bank2_valid; wire sdram_interface_bank2_ready; wire sdram_interface_bank2_we; wire [21:0] sdram_interface_bank2_addr; wire sdram_interface_bank2_lock; wire sdram_interface_bank2_wdata_ready; wire sdram_interface_bank2_rdata_valid; wire sdram_interface_bank3_valid; wire sdram_interface_bank3_ready; wire sdram_interface_bank3_we; wire [21:0] sdram_interface_bank3_addr; wire sdram_interface_bank3_lock; wire sdram_interface_bank3_wdata_ready; wire sdram_interface_bank3_rdata_valid; reg [15:0] sdram_interface_wdata = 16'd0; reg [1:0] sdram_interface_wdata_we = 2'd0; wire [15:0] sdram_interface_rdata; reg [12:0] sdram_dfi_p0_address = 13'd0; reg [1:0] sdram_dfi_p0_bank = 2'd0; reg sdram_dfi_p0_cas_n = 1'd1; reg sdram_dfi_p0_cs_n = 1'd1; reg sdram_dfi_p0_ras_n = 1'd1; reg sdram_dfi_p0_we_n = 1'd1; wire sdram_dfi_p0_cke; wire sdram_dfi_p0_odt; wire sdram_dfi_p0_reset_n; reg sdram_dfi_p0_act_n = 1'd1; wire [15:0] sdram_dfi_p0_wrdata; reg sdram_dfi_p0_wrdata_en = 1'd0; wire [1:0] sdram_dfi_p0_wrdata_mask; reg sdram_dfi_p0_rddata_en = 1'd0; wire [15:0] sdram_dfi_p0_rddata; wire sdram_dfi_p0_rddata_valid; reg sdram_cmd_valid = 1'd0; reg sdram_cmd_ready = 1'd0; reg sdram_cmd_last = 1'd0; reg [12:0] sdram_cmd_payload_a = 13'd0; reg [1:0] sdram_cmd_payload_ba = 2'd0; reg sdram_cmd_payload_cas = 1'd0; reg sdram_cmd_payload_ras = 1'd0; reg sdram_cmd_payload_we = 1'd0; reg sdram_cmd_payload_is_read = 1'd0; reg sdram_cmd_payload_is_write = 1'd0; wire sdram_wants_refresh; wire sdram_timer_wait; wire sdram_timer_done0; wire [9:0] sdram_timer_count0; wire sdram_timer_done1; reg [9:0] sdram_timer_count1 = 10'd781; wire sdram_postponer_req_i; reg sdram_postponer_req_o = 1'd0; reg sdram_postponer_count = 1'd0; reg sdram_sequencer_start0 = 1'd0; wire sdram_sequencer_done0; wire sdram_sequencer_start1; reg sdram_sequencer_done1 = 1'd0; reg [3:0] sdram_sequencer_counter = 4'd0; reg sdram_sequencer_count = 1'd0; wire sdram_bankmachine0_req_valid; wire sdram_bankmachine0_req_ready; wire sdram_bankmachine0_req_we; wire [21:0] sdram_bankmachine0_req_addr; wire sdram_bankmachine0_req_lock; reg sdram_bankmachine0_req_wdata_ready = 1'd0; reg sdram_bankmachine0_req_rdata_valid = 1'd0; wire sdram_bankmachine0_refresh_req; reg sdram_bankmachine0_refresh_gnt = 1'd0; reg sdram_bankmachine0_cmd_valid = 1'd0; reg sdram_bankmachine0_cmd_ready = 1'd0; reg [12:0] sdram_bankmachine0_cmd_payload_a = 13'd0; wire [1:0] sdram_bankmachine0_cmd_payload_ba; reg sdram_bankmachine0_cmd_payload_cas = 1'd0; reg sdram_bankmachine0_cmd_payload_ras = 1'd0; reg sdram_bankmachine0_cmd_payload_we = 1'd0; reg sdram_bankmachine0_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine0_cmd_payload_is_read = 1'd0; reg sdram_bankmachine0_cmd_payload_is_write = 1'd0; reg sdram_bankmachine0_auto_precharge = 1'd0; wire sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine0_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine0_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine0_cmd_buffer_lookahead_source_first; wire sdram_bankmachine0_cmd_buffer_lookahead_source_last; wire sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; reg [3:0] sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine0_cmd_buffer_lookahead_wrport_we; wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine0_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr; wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine0_cmd_buffer_sink_valid; wire sdram_bankmachine0_cmd_buffer_sink_ready; wire sdram_bankmachine0_cmd_buffer_sink_first; wire sdram_bankmachine0_cmd_buffer_sink_last; wire sdram_bankmachine0_cmd_buffer_sink_payload_we; wire [21:0] sdram_bankmachine0_cmd_buffer_sink_payload_addr; reg sdram_bankmachine0_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine0_cmd_buffer_source_ready; reg sdram_bankmachine0_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine0_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0; reg [21:0] sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0; reg [12:0] sdram_bankmachine0_row = 13'd0; reg sdram_bankmachine0_row_opened = 1'd0; wire sdram_bankmachine0_row_hit; reg sdram_bankmachine0_row_open = 1'd0; reg sdram_bankmachine0_row_close = 1'd0; reg sdram_bankmachine0_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine0_twtpcon_valid; (* no_retiming = "true" *) reg sdram_bankmachine0_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine0_twtpcon_count = 3'd0; wire sdram_bankmachine0_trccon_valid; (* no_retiming = "true" *) reg sdram_bankmachine0_trccon_ready = 1'd1; wire sdram_bankmachine0_trascon_valid; (* no_retiming = "true" *) reg sdram_bankmachine0_trascon_ready = 1'd1; wire sdram_bankmachine1_req_valid; wire sdram_bankmachine1_req_ready; wire sdram_bankmachine1_req_we; wire [21:0] sdram_bankmachine1_req_addr; wire sdram_bankmachine1_req_lock; reg sdram_bankmachine1_req_wdata_ready = 1'd0; reg sdram_bankmachine1_req_rdata_valid = 1'd0; wire sdram_bankmachine1_refresh_req; reg sdram_bankmachine1_refresh_gnt = 1'd0; reg sdram_bankmachine1_cmd_valid = 1'd0; reg sdram_bankmachine1_cmd_ready = 1'd0; reg [12:0] sdram_bankmachine1_cmd_payload_a = 13'd0; wire [1:0] sdram_bankmachine1_cmd_payload_ba; reg sdram_bankmachine1_cmd_payload_cas = 1'd0; reg sdram_bankmachine1_cmd_payload_ras = 1'd0; reg sdram_bankmachine1_cmd_payload_we = 1'd0; reg sdram_bankmachine1_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine1_cmd_payload_is_read = 1'd0; reg sdram_bankmachine1_cmd_payload_is_write = 1'd0; reg sdram_bankmachine1_auto_precharge = 1'd0; wire sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine1_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine1_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine1_cmd_buffer_lookahead_source_first; wire sdram_bankmachine1_cmd_buffer_lookahead_source_last; wire sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; reg [3:0] sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine1_cmd_buffer_lookahead_wrport_we; wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine1_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr; wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine1_cmd_buffer_sink_valid; wire sdram_bankmachine1_cmd_buffer_sink_ready; wire sdram_bankmachine1_cmd_buffer_sink_first; wire sdram_bankmachine1_cmd_buffer_sink_last; wire sdram_bankmachine1_cmd_buffer_sink_payload_we; wire [21:0] sdram_bankmachine1_cmd_buffer_sink_payload_addr; reg sdram_bankmachine1_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine1_cmd_buffer_source_ready; reg sdram_bankmachine1_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine1_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0; reg [21:0] sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0; reg [12:0] sdram_bankmachine1_row = 13'd0; reg sdram_bankmachine1_row_opened = 1'd0; wire sdram_bankmachine1_row_hit; reg sdram_bankmachine1_row_open = 1'd0; reg sdram_bankmachine1_row_close = 1'd0; reg sdram_bankmachine1_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine1_twtpcon_valid; (* no_retiming = "true" *) reg sdram_bankmachine1_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine1_twtpcon_count = 3'd0; wire sdram_bankmachine1_trccon_valid; (* no_retiming = "true" *) reg sdram_bankmachine1_trccon_ready = 1'd1; wire sdram_bankmachine1_trascon_valid; (* no_retiming = "true" *) reg sdram_bankmachine1_trascon_ready = 1'd1; wire sdram_bankmachine2_req_valid; wire sdram_bankmachine2_req_ready; wire sdram_bankmachine2_req_we; wire [21:0] sdram_bankmachine2_req_addr; wire sdram_bankmachine2_req_lock; reg sdram_bankmachine2_req_wdata_ready = 1'd0; reg sdram_bankmachine2_req_rdata_valid = 1'd0; wire sdram_bankmachine2_refresh_req; reg sdram_bankmachine2_refresh_gnt = 1'd0; reg sdram_bankmachine2_cmd_valid = 1'd0; reg sdram_bankmachine2_cmd_ready = 1'd0; reg [12:0] sdram_bankmachine2_cmd_payload_a = 13'd0; wire [1:0] sdram_bankmachine2_cmd_payload_ba; reg sdram_bankmachine2_cmd_payload_cas = 1'd0; reg sdram_bankmachine2_cmd_payload_ras = 1'd0; reg sdram_bankmachine2_cmd_payload_we = 1'd0; reg sdram_bankmachine2_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine2_cmd_payload_is_read = 1'd0; reg sdram_bankmachine2_cmd_payload_is_write = 1'd0; reg sdram_bankmachine2_auto_precharge = 1'd0; wire sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine2_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine2_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine2_cmd_buffer_lookahead_source_first; wire sdram_bankmachine2_cmd_buffer_lookahead_source_last; wire sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; reg [3:0] sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine2_cmd_buffer_lookahead_wrport_we; wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine2_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr; wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine2_cmd_buffer_sink_valid; wire sdram_bankmachine2_cmd_buffer_sink_ready; wire sdram_bankmachine2_cmd_buffer_sink_first; wire sdram_bankmachine2_cmd_buffer_sink_last; wire sdram_bankmachine2_cmd_buffer_sink_payload_we; wire [21:0] sdram_bankmachine2_cmd_buffer_sink_payload_addr; reg sdram_bankmachine2_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine2_cmd_buffer_source_ready; reg sdram_bankmachine2_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine2_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0; reg [21:0] sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0; reg [12:0] sdram_bankmachine2_row = 13'd0; reg sdram_bankmachine2_row_opened = 1'd0; wire sdram_bankmachine2_row_hit; reg sdram_bankmachine2_row_open = 1'd0; reg sdram_bankmachine2_row_close = 1'd0; reg sdram_bankmachine2_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine2_twtpcon_valid; (* no_retiming = "true" *) reg sdram_bankmachine2_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine2_twtpcon_count = 3'd0; wire sdram_bankmachine2_trccon_valid; (* no_retiming = "true" *) reg sdram_bankmachine2_trccon_ready = 1'd1; wire sdram_bankmachine2_trascon_valid; (* no_retiming = "true" *) reg sdram_bankmachine2_trascon_ready = 1'd1; wire sdram_bankmachine3_req_valid; wire sdram_bankmachine3_req_ready; wire sdram_bankmachine3_req_we; wire [21:0] sdram_bankmachine3_req_addr; wire sdram_bankmachine3_req_lock; reg sdram_bankmachine3_req_wdata_ready = 1'd0; reg sdram_bankmachine3_req_rdata_valid = 1'd0; wire sdram_bankmachine3_refresh_req; reg sdram_bankmachine3_refresh_gnt = 1'd0; reg sdram_bankmachine3_cmd_valid = 1'd0; reg sdram_bankmachine3_cmd_ready = 1'd0; reg [12:0] sdram_bankmachine3_cmd_payload_a = 13'd0; wire [1:0] sdram_bankmachine3_cmd_payload_ba; reg sdram_bankmachine3_cmd_payload_cas = 1'd0; reg sdram_bankmachine3_cmd_payload_ras = 1'd0; reg sdram_bankmachine3_cmd_payload_we = 1'd0; reg sdram_bankmachine3_cmd_payload_is_cmd = 1'd0; reg sdram_bankmachine3_cmd_payload_is_read = 1'd0; reg sdram_bankmachine3_cmd_payload_is_write = 1'd0; reg sdram_bankmachine3_auto_precharge = 1'd0; wire sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; wire sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; reg sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; reg sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; wire sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; wire sdram_bankmachine3_cmd_buffer_lookahead_source_valid; wire sdram_bankmachine3_cmd_buffer_lookahead_source_ready; wire sdram_bankmachine3_cmd_buffer_lookahead_source_first; wire sdram_bankmachine3_cmd_buffer_lookahead_source_last; wire sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; reg [3:0] sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0; reg sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0; reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0; reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0; wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; wire sdram_bankmachine3_cmd_buffer_lookahead_wrport_we; wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; wire sdram_bankmachine3_cmd_buffer_lookahead_do_read; wire [2:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr; wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; wire sdram_bankmachine3_cmd_buffer_sink_valid; wire sdram_bankmachine3_cmd_buffer_sink_ready; wire sdram_bankmachine3_cmd_buffer_sink_first; wire sdram_bankmachine3_cmd_buffer_sink_last; wire sdram_bankmachine3_cmd_buffer_sink_payload_we; wire [21:0] sdram_bankmachine3_cmd_buffer_sink_payload_addr; reg sdram_bankmachine3_cmd_buffer_source_valid = 1'd0; wire sdram_bankmachine3_cmd_buffer_source_ready; reg sdram_bankmachine3_cmd_buffer_source_first = 1'd0; reg sdram_bankmachine3_cmd_buffer_source_last = 1'd0; reg sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0; reg [21:0] sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0; reg [12:0] sdram_bankmachine3_row = 13'd0; reg sdram_bankmachine3_row_opened = 1'd0; wire sdram_bankmachine3_row_hit; reg sdram_bankmachine3_row_open = 1'd0; reg sdram_bankmachine3_row_close = 1'd0; reg sdram_bankmachine3_row_col_n_addr_sel = 1'd0; wire sdram_bankmachine3_twtpcon_valid; (* no_retiming = "true" *) reg sdram_bankmachine3_twtpcon_ready = 1'd0; reg [2:0] sdram_bankmachine3_twtpcon_count = 3'd0; wire sdram_bankmachine3_trccon_valid; (* no_retiming = "true" *) reg sdram_bankmachine3_trccon_ready = 1'd1; wire sdram_bankmachine3_trascon_valid; (* no_retiming = "true" *) reg sdram_bankmachine3_trascon_ready = 1'd1; wire sdram_ras_allowed; wire sdram_cas_allowed; reg sdram_choose_cmd_want_reads = 1'd0; reg sdram_choose_cmd_want_writes = 1'd0; reg sdram_choose_cmd_want_cmds = 1'd0; reg sdram_choose_cmd_want_activates = 1'd0; wire sdram_choose_cmd_cmd_valid; reg sdram_choose_cmd_cmd_ready = 1'd0; wire [12:0] sdram_choose_cmd_cmd_payload_a; wire [1:0] sdram_choose_cmd_cmd_payload_ba; reg sdram_choose_cmd_cmd_payload_cas = 1'd0; reg sdram_choose_cmd_cmd_payload_ras = 1'd0; reg sdram_choose_cmd_cmd_payload_we = 1'd0; wire sdram_choose_cmd_cmd_payload_is_cmd; wire sdram_choose_cmd_cmd_payload_is_read; wire sdram_choose_cmd_cmd_payload_is_write; reg [3:0] sdram_choose_cmd_valids = 4'd0; wire [3:0] sdram_choose_cmd_request; reg [1:0] sdram_choose_cmd_grant = 2'd0; wire sdram_choose_cmd_ce; reg sdram_choose_req_want_reads = 1'd0; reg sdram_choose_req_want_writes = 1'd0; wire sdram_choose_req_want_cmds; reg sdram_choose_req_want_activates = 1'd0; wire sdram_choose_req_cmd_valid; reg sdram_choose_req_cmd_ready = 1'd0; wire [12:0] sdram_choose_req_cmd_payload_a; wire [1:0] sdram_choose_req_cmd_payload_ba; reg sdram_choose_req_cmd_payload_cas = 1'd0; reg sdram_choose_req_cmd_payload_ras = 1'd0; reg sdram_choose_req_cmd_payload_we = 1'd0; wire sdram_choose_req_cmd_payload_is_cmd; wire sdram_choose_req_cmd_payload_is_read; wire sdram_choose_req_cmd_payload_is_write; reg [3:0] sdram_choose_req_valids = 4'd0; wire [3:0] sdram_choose_req_request; reg [1:0] sdram_choose_req_grant = 2'd0; wire sdram_choose_req_ce; reg [12:0] sdram_nop_a = 13'd0; reg [1:0] sdram_nop_ba = 2'd0; reg [1:0] sdram_steerer_sel = 2'd0; reg sdram_steerer0 = 1'd1; reg sdram_steerer1 = 1'd1; wire sdram_trrdcon_valid; (* no_retiming = "true" *) reg sdram_trrdcon_ready = 1'd1; wire sdram_tfawcon_valid; (* no_retiming = "true" *) reg sdram_tfawcon_ready = 1'd1; wire sdram_tccdcon_valid; (* no_retiming = "true" *) reg sdram_tccdcon_ready = 1'd0; reg sdram_tccdcon_count = 1'd0; wire sdram_twtrcon_valid; (* no_retiming = "true" *) reg sdram_twtrcon_ready = 1'd0; reg [2:0] sdram_twtrcon_count = 3'd0; wire sdram_read_available; wire sdram_write_available; reg sdram_en0 = 1'd0; wire sdram_max_time0; reg [4:0] sdram_time0 = 5'd0; reg sdram_en1 = 1'd0; wire sdram_max_time1; reg [3:0] sdram_time1 = 4'd0; wire sdram_go_to_refresh; wire port_flush; wire port_cmd_valid; wire port_cmd_ready; wire port_cmd_last; wire port_cmd_payload_we; wire [23:0] port_cmd_payload_addr; wire port_wdata_valid; wire port_wdata_ready; wire [15:0] port_wdata_payload_data; wire [1:0] port_wdata_payload_we; wire port_rdata_valid; wire port_rdata_ready; wire [15:0] port_rdata_payload_data; wire [29:0] wb_sdram_adr; wire [31:0] wb_sdram_dat_w; wire [31:0] wb_sdram_dat_r; wire [3:0] wb_sdram_sel; wire wb_sdram_cyc; wire wb_sdram_stb; reg wb_sdram_ack = 1'd0; wire wb_sdram_we; wire [2:0] wb_sdram_cti; wire [1:0] wb_sdram_bte; reg wb_sdram_err = 1'd0; reg [29:0] litedram_wb_adr = 30'd0; reg [15:0] litedram_wb_dat_w = 16'd0; wire [15:0] litedram_wb_dat_r; reg [1:0] litedram_wb_sel = 2'd0; reg litedram_wb_cyc = 1'd0; reg litedram_wb_stb = 1'd0; wire litedram_wb_ack; reg litedram_wb_we = 1'd0; reg converter_skip = 1'd0; reg converter_counter = 1'd0; wire converter_reset; reg [31:0] converter_dat_r = 32'd0; reg cmd_consumed = 1'd0; reg wdata_consumed = 1'd0; wire ack_cmd; wire ack_wdata; wire ack_rdata; (* ram_style = "distributed" *) reg [31:0] uart_phy_storage = 32'd9895604; reg uart_phy_re = 1'd0; wire uart_phy_sink_valid; reg uart_phy_sink_ready = 1'd0; wire uart_phy_sink_first; wire uart_phy_sink_last; wire [7:0] uart_phy_sink_payload_data; reg uart_phy_uart_clk_txen = 1'd0; reg [31:0] uart_phy_phase_accumulator_tx = 32'd0; reg [7:0] uart_phy_tx_reg = 8'd0; reg [3:0] uart_phy_tx_bitcount = 4'd0; reg uart_phy_tx_busy = 1'd0; reg uart_phy_source_valid = 1'd0; wire uart_phy_source_ready; reg uart_phy_source_first = 1'd0; reg uart_phy_source_last = 1'd0; reg [7:0] uart_phy_source_payload_data = 8'd0; reg uart_phy_uart_clk_rxen = 1'd0; reg [31:0] uart_phy_phase_accumulator_rx = 32'd0; wire uart_phy_rx; reg uart_phy_rx_r = 1'd0; reg [7:0] uart_phy_rx_reg = 8'd0; reg [3:0] uart_phy_rx_bitcount = 4'd0; reg uart_phy_rx_busy = 1'd0; wire rxtx_re; wire [7:0] rxtx_r; wire rxtx_we; wire [7:0] rxtx_w; wire txfull_status; wire txfull_we; wire rxempty_status; wire rxempty_we; wire irq; wire tx_status; reg tx_pending = 1'd0; wire tx_trigger; reg tx_clear = 1'd0; reg tx_old_trigger = 1'd0; wire rx_status; reg rx_pending = 1'd0; wire rx_trigger; reg rx_clear = 1'd0; reg rx_old_trigger = 1'd0; wire eventmanager_status_re; wire [1:0] eventmanager_status_r; wire eventmanager_status_we; reg [1:0] eventmanager_status_w = 2'd0; wire eventmanager_pending_re; wire [1:0] eventmanager_pending_r; wire eventmanager_pending_we; reg [1:0] eventmanager_pending_w = 2'd0; (* ram_style = "distributed" *) reg [1:0] eventmanager_storage = 2'd0; reg eventmanager_re = 1'd0; wire txempty_status; wire txempty_we; wire rxfull_status; wire rxfull_we; wire uart_sink_valid; wire uart_sink_ready; wire uart_sink_first; wire uart_sink_last; wire [7:0] uart_sink_payload_data; wire uart_source_valid; wire uart_source_ready; wire uart_source_first; wire uart_source_last; wire [7:0] uart_source_payload_data; wire tx_fifo_sink_valid; wire tx_fifo_sink_ready; reg tx_fifo_sink_first = 1'd0; reg tx_fifo_sink_last = 1'd0; wire [7:0] tx_fifo_sink_payload_data; wire tx_fifo_source_valid; wire tx_fifo_source_ready; wire tx_fifo_source_first; wire tx_fifo_source_last; wire [7:0] tx_fifo_source_payload_data; wire tx_fifo_re; reg tx_fifo_readable = 1'd0; wire tx_fifo_syncfifo_we; wire tx_fifo_syncfifo_writable; wire tx_fifo_syncfifo_re; wire tx_fifo_syncfifo_readable; wire [9:0] tx_fifo_syncfifo_din; wire [9:0] tx_fifo_syncfifo_dout; reg [4:0] tx_fifo_level0 = 5'd0; reg tx_fifo_replace = 1'd0; reg [3:0] tx_fifo_produce = 4'd0; reg [3:0] tx_fifo_consume = 4'd0; reg [3:0] tx_fifo_wrport_adr = 4'd0; wire [9:0] tx_fifo_wrport_dat_r; wire tx_fifo_wrport_we; wire [9:0] tx_fifo_wrport_dat_w; wire tx_fifo_do_read; wire [3:0] tx_fifo_rdport_adr; wire [9:0] tx_fifo_rdport_dat_r; wire tx_fifo_rdport_re; wire [4:0] tx_fifo_level1; wire [7:0] tx_fifo_fifo_in_payload_data; wire tx_fifo_fifo_in_first; wire tx_fifo_fifo_in_last; wire [7:0] tx_fifo_fifo_out_payload_data; wire tx_fifo_fifo_out_first; wire tx_fifo_fifo_out_last; wire rx_fifo_sink_valid; wire rx_fifo_sink_ready; wire rx_fifo_sink_first; wire rx_fifo_sink_last; wire [7:0] rx_fifo_sink_payload_data; wire rx_fifo_source_valid; wire rx_fifo_source_ready; wire rx_fifo_source_first; wire rx_fifo_source_last; wire [7:0] rx_fifo_source_payload_data; wire rx_fifo_re; reg rx_fifo_readable = 1'd0; wire rx_fifo_syncfifo_we; wire rx_fifo_syncfifo_writable; wire rx_fifo_syncfifo_re; wire rx_fifo_syncfifo_readable; wire [9:0] rx_fifo_syncfifo_din; wire [9:0] rx_fifo_syncfifo_dout; reg [4:0] rx_fifo_level0 = 5'd0; reg rx_fifo_replace = 1'd0; reg [3:0] rx_fifo_produce = 4'd0; reg [3:0] rx_fifo_consume = 4'd0; reg [3:0] rx_fifo_wrport_adr = 4'd0; wire [9:0] rx_fifo_wrport_dat_r; wire rx_fifo_wrport_we; wire [9:0] rx_fifo_wrport_dat_w; wire rx_fifo_do_read; wire [3:0] rx_fifo_rdport_adr; wire [9:0] rx_fifo_rdport_dat_r; wire rx_fifo_rdport_re; wire [4:0] rx_fifo_level1; wire [7:0] rx_fifo_fifo_in_payload_data; wire rx_fifo_fifo_in_first; wire rx_fifo_fifo_in_last; wire [7:0] rx_fifo_fifo_out_payload_data; wire rx_fifo_fifo_out_first; wire rx_fifo_fifo_out_last; reg reset = 1'd0; (* ram_style = "distributed" *) reg [7:0] gpio0_oe_storage = 8'd0; reg gpio0_oe_re = 1'd0; reg [7:0] gpio0_status = 8'd0; wire gpio0_we; (* ram_style = "distributed" *) reg [7:0] gpio0_out_storage = 8'd0; reg gpio0_out_re = 1'd0; reg [7:0] gpio0_pads_gpio0i = 8'd0; reg [7:0] gpio0_pads_gpio0o = 8'd0; reg [7:0] gpio0_pads_gpio0oe = 8'd0; (* ram_style = "distributed" *) reg [7:0] gpio1_oe_storage = 8'd0; reg gpio1_oe_re = 1'd0; reg [7:0] gpio1_status = 8'd0; wire gpio1_we; (* ram_style = "distributed" *) reg [7:0] gpio1_out_storage = 8'd0; reg gpio1_out_re = 1'd0; reg [7:0] gpio1_pads_gpio1i = 8'd0; reg [7:0] gpio1_pads_gpio1o = 8'd0; reg [7:0] gpio1_pads_gpio1oe = 8'd0; reg [2:0] eint_tmp = 3'd0; wire [39:0] nc_1; reg [39:0] dummy = 40'd0; wire i2c_scl_1; wire i2c_oe; wire i2c_sda0; (* ram_style = "distributed" *) reg [2:0] i2c_storage = 3'd0; reg i2c_re = 1'd0; wire i2c_sda1; wire i2c_status; wire i2c_we; reg subfragments_converter0_state = 1'd0; reg subfragments_converter0_next_state = 1'd0; reg libresocsim_converter0_counter_subfragments_converter0_next_value = 1'd0; reg libresocsim_converter0_counter_subfragments_converter0_next_value_ce = 1'd0; reg subfragments_converter1_state = 1'd0; reg subfragments_converter1_next_state = 1'd0; reg libresocsim_converter1_counter_subfragments_converter1_next_value = 1'd0; reg libresocsim_converter1_counter_subfragments_converter1_next_value_ce = 1'd0; reg [1:0] subfragments_refresher_state = 2'd0; reg [1:0] subfragments_refresher_next_state = 2'd0; reg [2:0] subfragments_bankmachine0_state = 3'd0; reg [2:0] subfragments_bankmachine0_next_state = 3'd0; reg [2:0] subfragments_bankmachine1_state = 3'd0; reg [2:0] subfragments_bankmachine1_next_state = 3'd0; reg [2:0] subfragments_bankmachine2_state = 3'd0; reg [2:0] subfragments_bankmachine2_next_state = 3'd0; reg [2:0] subfragments_bankmachine3_state = 3'd0; reg [2:0] subfragments_bankmachine3_next_state = 3'd0; reg [2:0] subfragments_multiplexer_state = 3'd0; reg [2:0] subfragments_multiplexer_next_state = 3'd0; wire subfragments_roundrobin0_request; wire subfragments_roundrobin0_grant; wire subfragments_roundrobin0_ce; wire subfragments_roundrobin1_request; wire subfragments_roundrobin1_grant; wire subfragments_roundrobin1_ce; wire subfragments_roundrobin2_request; wire subfragments_roundrobin2_grant; wire subfragments_roundrobin2_ce; wire subfragments_roundrobin3_request; wire subfragments_roundrobin3_grant; wire subfragments_roundrobin3_ce; reg subfragments_locked0 = 1'd0; reg subfragments_locked1 = 1'd0; reg subfragments_locked2 = 1'd0; reg subfragments_locked3 = 1'd0; reg subfragments_new_master_wdata_ready = 1'd0; reg subfragments_new_master_rdata_valid0 = 1'd0; reg subfragments_new_master_rdata_valid1 = 1'd0; reg subfragments_new_master_rdata_valid2 = 1'd0; reg subfragments_new_master_rdata_valid3 = 1'd0; reg subfragments_state = 1'd0; reg subfragments_next_state = 1'd0; reg converter_counter_subfragments_next_value = 1'd0; reg converter_counter_subfragments_next_value_ce = 1'd0; reg [12:0] libresocsim_libresocsim_adr = 13'd0; reg libresocsim_libresocsim_we = 1'd0; reg [7:0] libresocsim_libresocsim_dat_w = 8'd0; wire [7:0] libresocsim_libresocsim_dat_r; wire [29:0] libresocsim_libresocsim_wishbone_adr; wire [31:0] libresocsim_libresocsim_wishbone_dat_w; reg [31:0] libresocsim_libresocsim_wishbone_dat_r = 32'd0; wire [3:0] libresocsim_libresocsim_wishbone_sel; wire libresocsim_libresocsim_wishbone_cyc; wire libresocsim_libresocsim_wishbone_stb; reg libresocsim_libresocsim_wishbone_ack = 1'd0; wire libresocsim_libresocsim_wishbone_we; wire [2:0] libresocsim_libresocsim_wishbone_cti; wire [1:0] libresocsim_libresocsim_wishbone_bte; reg libresocsim_libresocsim_wishbone_err = 1'd0; wire [29:0] libresocsim_shared_adr; wire [31:0] libresocsim_shared_dat_w; reg [31:0] libresocsim_shared_dat_r = 32'd0; wire [3:0] libresocsim_shared_sel; wire libresocsim_shared_cyc; wire libresocsim_shared_stb; reg libresocsim_shared_ack = 1'd0; wire libresocsim_shared_we; wire [2:0] libresocsim_shared_cti; wire [1:0] libresocsim_shared_bte; wire libresocsim_shared_err; wire [2:0] libresocsim_request; reg [1:0] libresocsim_grant = 2'd0; reg [5:0] libresocsim_slave_sel = 6'd0; reg [5:0] libresocsim_slave_sel_r = 6'd0; reg libresocsim_error = 1'd0; wire libresocsim_wait; wire libresocsim_done; reg [19:0] libresocsim_count = 20'd1000000; wire [12:0] libresocsim_interface0_bank_bus_adr; wire libresocsim_interface0_bank_bus_we; wire [7:0] libresocsim_interface0_bank_bus_dat_w; reg [7:0] libresocsim_interface0_bank_bus_dat_r = 8'd0; wire libresocsim_csrbank0_reset0_re; wire libresocsim_csrbank0_reset0_r; wire libresocsim_csrbank0_reset0_we; wire libresocsim_csrbank0_reset0_w; wire libresocsim_csrbank0_scratch3_re; wire [7:0] libresocsim_csrbank0_scratch3_r; wire libresocsim_csrbank0_scratch3_we; wire [7:0] libresocsim_csrbank0_scratch3_w; wire libresocsim_csrbank0_scratch2_re; wire [7:0] libresocsim_csrbank0_scratch2_r; wire libresocsim_csrbank0_scratch2_we; wire [7:0] libresocsim_csrbank0_scratch2_w; wire libresocsim_csrbank0_scratch1_re; wire [7:0] libresocsim_csrbank0_scratch1_r; wire libresocsim_csrbank0_scratch1_we; wire [7:0] libresocsim_csrbank0_scratch1_w; wire libresocsim_csrbank0_scratch0_re; wire [7:0] libresocsim_csrbank0_scratch0_r; wire libresocsim_csrbank0_scratch0_we; wire [7:0] libresocsim_csrbank0_scratch0_w; wire libresocsim_csrbank0_bus_errors3_re; wire [7:0] libresocsim_csrbank0_bus_errors3_r; wire libresocsim_csrbank0_bus_errors3_we; wire [7:0] libresocsim_csrbank0_bus_errors3_w; wire libresocsim_csrbank0_bus_errors2_re; wire [7:0] libresocsim_csrbank0_bus_errors2_r; wire libresocsim_csrbank0_bus_errors2_we; wire [7:0] libresocsim_csrbank0_bus_errors2_w; wire libresocsim_csrbank0_bus_errors1_re; wire [7:0] libresocsim_csrbank0_bus_errors1_r; wire libresocsim_csrbank0_bus_errors1_we; wire [7:0] libresocsim_csrbank0_bus_errors1_w; wire libresocsim_csrbank0_bus_errors0_re; wire [7:0] libresocsim_csrbank0_bus_errors0_r; wire libresocsim_csrbank0_bus_errors0_we; wire [7:0] libresocsim_csrbank0_bus_errors0_w; wire libresocsim_csrbank0_sel; wire [12:0] libresocsim_interface1_bank_bus_adr; wire libresocsim_interface1_bank_bus_we; wire [7:0] libresocsim_interface1_bank_bus_dat_w; reg [7:0] libresocsim_interface1_bank_bus_dat_r = 8'd0; wire libresocsim_csrbank1_oe0_re; wire [7:0] libresocsim_csrbank1_oe0_r; wire libresocsim_csrbank1_oe0_we; wire [7:0] libresocsim_csrbank1_oe0_w; wire libresocsim_csrbank1_in_re; wire [7:0] libresocsim_csrbank1_in_r; wire libresocsim_csrbank1_in_we; wire [7:0] libresocsim_csrbank1_in_w; wire libresocsim_csrbank1_out0_re; wire [7:0] libresocsim_csrbank1_out0_r; wire libresocsim_csrbank1_out0_we; wire [7:0] libresocsim_csrbank1_out0_w; wire libresocsim_csrbank1_sel; wire [12:0] libresocsim_interface2_bank_bus_adr; wire libresocsim_interface2_bank_bus_we; wire [7:0] libresocsim_interface2_bank_bus_dat_w; reg [7:0] libresocsim_interface2_bank_bus_dat_r = 8'd0; wire libresocsim_csrbank2_oe0_re; wire [7:0] libresocsim_csrbank2_oe0_r; wire libresocsim_csrbank2_oe0_we; wire [7:0] libresocsim_csrbank2_oe0_w; wire libresocsim_csrbank2_in_re; wire [7:0] libresocsim_csrbank2_in_r; wire libresocsim_csrbank2_in_we; wire [7:0] libresocsim_csrbank2_in_w; wire libresocsim_csrbank2_out0_re; wire [7:0] libresocsim_csrbank2_out0_r; wire libresocsim_csrbank2_out0_we; wire [7:0] libresocsim_csrbank2_out0_w; wire libresocsim_csrbank2_sel; wire [12:0] libresocsim_interface3_bank_bus_adr; wire libresocsim_interface3_bank_bus_we; wire [7:0] libresocsim_interface3_bank_bus_dat_w; reg [7:0] libresocsim_interface3_bank_bus_dat_r = 8'd0; wire libresocsim_csrbank3_w0_re; wire [2:0] libresocsim_csrbank3_w0_r; wire libresocsim_csrbank3_w0_we; wire [2:0] libresocsim_csrbank3_w0_w; wire libresocsim_csrbank3_r_re; wire libresocsim_csrbank3_r_r; wire libresocsim_csrbank3_r_we; wire libresocsim_csrbank3_r_w; wire libresocsim_csrbank3_sel; wire [12:0] libresocsim_interface4_bank_bus_adr; wire libresocsim_interface4_bank_bus_we; wire [7:0] libresocsim_interface4_bank_bus_dat_w; reg [7:0] libresocsim_interface4_bank_bus_dat_r = 8'd0; wire libresocsim_csrbank4_dfii_control0_re; wire [3:0] libresocsim_csrbank4_dfii_control0_r; wire libresocsim_csrbank4_dfii_control0_we; wire [3:0] libresocsim_csrbank4_dfii_control0_w; wire libresocsim_csrbank4_dfii_pi0_command0_re; wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_r; wire libresocsim_csrbank4_dfii_pi0_command0_we; wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_w; wire libresocsim_csrbank4_dfii_pi0_address1_re; wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_r; wire libresocsim_csrbank4_dfii_pi0_address1_we; wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_w; wire libresocsim_csrbank4_dfii_pi0_address0_re; wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_r; wire libresocsim_csrbank4_dfii_pi0_address0_we; wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_w; wire libresocsim_csrbank4_dfii_pi0_baddress0_re; wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_r; wire libresocsim_csrbank4_dfii_pi0_baddress0_we; wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_w; wire libresocsim_csrbank4_dfii_pi0_wrdata1_re; wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_r; wire libresocsim_csrbank4_dfii_pi0_wrdata1_we; wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_w; wire libresocsim_csrbank4_dfii_pi0_wrdata0_re; wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_r; wire libresocsim_csrbank4_dfii_pi0_wrdata0_we; wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_w; wire libresocsim_csrbank4_dfii_pi0_rddata1_re; wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_r; wire libresocsim_csrbank4_dfii_pi0_rddata1_we; wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_w; wire libresocsim_csrbank4_dfii_pi0_rddata0_re; wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_r; wire libresocsim_csrbank4_dfii_pi0_rddata0_we; wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_w; wire libresocsim_csrbank4_sel; wire [12:0] libresocsim_interface5_bank_bus_adr; wire libresocsim_interface5_bank_bus_we; wire [7:0] libresocsim_interface5_bank_bus_dat_w; reg [7:0] libresocsim_interface5_bank_bus_dat_r = 8'd0; wire libresocsim_csrbank5_load3_re; wire [7:0] libresocsim_csrbank5_load3_r; wire libresocsim_csrbank5_load3_we; wire [7:0] libresocsim_csrbank5_load3_w; wire libresocsim_csrbank5_load2_re; wire [7:0] libresocsim_csrbank5_load2_r; wire libresocsim_csrbank5_load2_we; wire [7:0] libresocsim_csrbank5_load2_w; wire libresocsim_csrbank5_load1_re; wire [7:0] libresocsim_csrbank5_load1_r; wire libresocsim_csrbank5_load1_we; wire [7:0] libresocsim_csrbank5_load1_w; wire libresocsim_csrbank5_load0_re; wire [7:0] libresocsim_csrbank5_load0_r; wire libresocsim_csrbank5_load0_we; wire [7:0] libresocsim_csrbank5_load0_w; wire libresocsim_csrbank5_reload3_re; wire [7:0] libresocsim_csrbank5_reload3_r; wire libresocsim_csrbank5_reload3_we; wire [7:0] libresocsim_csrbank5_reload3_w; wire libresocsim_csrbank5_reload2_re; wire [7:0] libresocsim_csrbank5_reload2_r; wire libresocsim_csrbank5_reload2_we; wire [7:0] libresocsim_csrbank5_reload2_w; wire libresocsim_csrbank5_reload1_re; wire [7:0] libresocsim_csrbank5_reload1_r; wire libresocsim_csrbank5_reload1_we; wire [7:0] libresocsim_csrbank5_reload1_w; wire libresocsim_csrbank5_reload0_re; wire [7:0] libresocsim_csrbank5_reload0_r; wire libresocsim_csrbank5_reload0_we; wire [7:0] libresocsim_csrbank5_reload0_w; wire libresocsim_csrbank5_en0_re; wire libresocsim_csrbank5_en0_r; wire libresocsim_csrbank5_en0_we; wire libresocsim_csrbank5_en0_w; wire libresocsim_csrbank5_update_value0_re; wire libresocsim_csrbank5_update_value0_r; wire libresocsim_csrbank5_update_value0_we; wire libresocsim_csrbank5_update_value0_w; wire libresocsim_csrbank5_value3_re; wire [7:0] libresocsim_csrbank5_value3_r; wire libresocsim_csrbank5_value3_we; wire [7:0] libresocsim_csrbank5_value3_w; wire libresocsim_csrbank5_value2_re; wire [7:0] libresocsim_csrbank5_value2_r; wire libresocsim_csrbank5_value2_we; wire [7:0] libresocsim_csrbank5_value2_w; wire libresocsim_csrbank5_value1_re; wire [7:0] libresocsim_csrbank5_value1_r; wire libresocsim_csrbank5_value1_we; wire [7:0] libresocsim_csrbank5_value1_w; wire libresocsim_csrbank5_value0_re; wire [7:0] libresocsim_csrbank5_value0_r; wire libresocsim_csrbank5_value0_we; wire [7:0] libresocsim_csrbank5_value0_w; wire libresocsim_csrbank5_ev_enable0_re; wire libresocsim_csrbank5_ev_enable0_r; wire libresocsim_csrbank5_ev_enable0_we; wire libresocsim_csrbank5_ev_enable0_w; wire libresocsim_csrbank5_sel; wire [12:0] libresocsim_interface6_bank_bus_adr; wire libresocsim_interface6_bank_bus_we; wire [7:0] libresocsim_interface6_bank_bus_dat_w; reg [7:0] libresocsim_interface6_bank_bus_dat_r = 8'd0; wire libresocsim_csrbank6_txfull_re; wire libresocsim_csrbank6_txfull_r; wire libresocsim_csrbank6_txfull_we; wire libresocsim_csrbank6_txfull_w; wire libresocsim_csrbank6_rxempty_re; wire libresocsim_csrbank6_rxempty_r; wire libresocsim_csrbank6_rxempty_we; wire libresocsim_csrbank6_rxempty_w; wire libresocsim_csrbank6_ev_enable0_re; wire [1:0] libresocsim_csrbank6_ev_enable0_r; wire libresocsim_csrbank6_ev_enable0_we; wire [1:0] libresocsim_csrbank6_ev_enable0_w; wire libresocsim_csrbank6_txempty_re; wire libresocsim_csrbank6_txempty_r; wire libresocsim_csrbank6_txempty_we; wire libresocsim_csrbank6_txempty_w; wire libresocsim_csrbank6_rxfull_re; wire libresocsim_csrbank6_rxfull_r; wire libresocsim_csrbank6_rxfull_we; wire libresocsim_csrbank6_rxfull_w; wire libresocsim_csrbank6_sel; wire [12:0] libresocsim_interface7_bank_bus_adr; wire libresocsim_interface7_bank_bus_we; wire [7:0] libresocsim_interface7_bank_bus_dat_w; reg [7:0] libresocsim_interface7_bank_bus_dat_r = 8'd0; wire libresocsim_csrbank7_tuning_word3_re; wire [7:0] libresocsim_csrbank7_tuning_word3_r; wire libresocsim_csrbank7_tuning_word3_we; wire [7:0] libresocsim_csrbank7_tuning_word3_w; wire libresocsim_csrbank7_tuning_word2_re; wire [7:0] libresocsim_csrbank7_tuning_word2_r; wire libresocsim_csrbank7_tuning_word2_we; wire [7:0] libresocsim_csrbank7_tuning_word2_w; wire libresocsim_csrbank7_tuning_word1_re; wire [7:0] libresocsim_csrbank7_tuning_word1_r; wire libresocsim_csrbank7_tuning_word1_we; wire [7:0] libresocsim_csrbank7_tuning_word1_w; wire libresocsim_csrbank7_tuning_word0_re; wire [7:0] libresocsim_csrbank7_tuning_word0_r; wire libresocsim_csrbank7_tuning_word0_we; wire [7:0] libresocsim_csrbank7_tuning_word0_w; wire libresocsim_csrbank7_sel; wire [12:0] libresocsim_csr_interconnect_adr; wire libresocsim_csr_interconnect_we; wire [7:0] libresocsim_csr_interconnect_dat_w; wire [7:0] libresocsim_csr_interconnect_dat_r; reg [1:0] libresocsim_state = 2'd0; reg [1:0] libresocsim_next_state = 2'd0; reg [7:0] libresocsim_libresocsim_dat_w_libresocsim_next_value0 = 8'd0; reg libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 = 1'd0; reg [12:0] libresocsim_libresocsim_adr_libresocsim_next_value1 = 13'd0; reg libresocsim_libresocsim_adr_libresocsim_next_value_ce1 = 1'd0; reg libresocsim_libresocsim_we_libresocsim_next_value2 = 1'd0; reg libresocsim_libresocsim_we_libresocsim_next_value_ce2 = 1'd0; reg rhs_array_muxed0 = 1'd0; reg [12:0] rhs_array_muxed1 = 13'd0; reg [1:0] rhs_array_muxed2 = 2'd0; reg rhs_array_muxed3 = 1'd0; reg rhs_array_muxed4 = 1'd0; reg rhs_array_muxed5 = 1'd0; reg t_array_muxed0 = 1'd0; reg t_array_muxed1 = 1'd0; reg t_array_muxed2 = 1'd0; reg rhs_array_muxed6 = 1'd0; reg [12:0] rhs_array_muxed7 = 13'd0; reg [1:0] rhs_array_muxed8 = 2'd0; reg rhs_array_muxed9 = 1'd0; reg rhs_array_muxed10 = 1'd0; reg rhs_array_muxed11 = 1'd0; reg t_array_muxed3 = 1'd0; reg t_array_muxed4 = 1'd0; reg t_array_muxed5 = 1'd0; reg [21:0] rhs_array_muxed12 = 22'd0; reg rhs_array_muxed13 = 1'd0; reg rhs_array_muxed14 = 1'd0; reg [21:0] rhs_array_muxed15 = 22'd0; reg rhs_array_muxed16 = 1'd0; reg rhs_array_muxed17 = 1'd0; reg [21:0] rhs_array_muxed18 = 22'd0; reg rhs_array_muxed19 = 1'd0; reg rhs_array_muxed20 = 1'd0; reg [21:0] rhs_array_muxed21 = 22'd0; reg rhs_array_muxed22 = 1'd0; reg rhs_array_muxed23 = 1'd0; reg [29:0] rhs_array_muxed24 = 30'd0; reg [31:0] rhs_array_muxed25 = 32'd0; reg [3:0] rhs_array_muxed26 = 4'd0; reg rhs_array_muxed27 = 1'd0; reg rhs_array_muxed28 = 1'd0; reg rhs_array_muxed29 = 1'd0; reg [2:0] rhs_array_muxed30 = 3'd0; reg [1:0] rhs_array_muxed31 = 2'd0; reg [1:0] array_muxed0 = 2'd0; reg [12:0] array_muxed1 = 13'd0; reg array_muxed2 = 1'd0; reg array_muxed3 = 1'd0; reg array_muxed4 = 1'd0; reg array_muxed5 = 1'd0; reg array_muxed6 = 1'd0; wire sdrio_clk; wire sdrio_clk_1; wire sdrio_clk_2; wire sdrio_clk_3; wire sdrio_clk_4; wire sdrio_clk_5; wire sdrio_clk_6; wire sdrio_clk_7; wire sdrio_clk_8; wire sdrio_clk_9; wire sdrio_clk_10; wire sdrio_clk_11; wire sdrio_clk_12; wire sdrio_clk_13; wire sdrio_clk_14; wire sdrio_clk_15; wire sdrio_clk_16; wire sdrio_clk_17; wire sdrio_clk_18; wire sdrio_clk_19; wire sdrio_clk_20; wire sdrio_clk_21; wire sdrio_clk_22; wire sdrio_clk_23; wire sdrio_clk_24; wire sdrio_clk_25; wire sdrio_clk_26; wire sdrio_clk_27; wire sdrio_clk_28; wire sdrio_clk_29; wire sdrio_clk_30; wire sdrio_clk_31; wire sdrio_clk_32; wire sdrio_clk_33; wire sdrio_clk_34; wire sdrio_clk_35; wire sdrio_clk_36; wire sdrio_clk_37; wire sdrio_clk_38; wire sdrio_clk_39; wire sdrio_clk_40; wire sdrio_clk_41; wire sdrio_clk_42; wire sdrio_clk_43; wire sdrio_clk_44; wire sdrio_clk_45; wire sdrio_clk_46; wire sdrio_clk_47; wire sdrio_clk_48; wire sdrio_clk_49; wire sdrio_clk_50; wire sdrio_clk_51; wire sdrio_clk_52; wire sdrio_clk_53; wire sdrio_clk_54; wire sdrio_clk_55; wire sdrio_clk_56; wire sdrio_clk_57; wire sdrio_clk_58; wire sdrio_clk_59; wire sdrio_clk_60; wire sdrio_clk_61; wire sdrio_clk_62; wire sdrio_clk_63; wire sdrio_clk_64; wire sdrio_clk_65; wire sdrio_clk_66; wire sdrio_clk_67; wire sdrio_clk_68; wire sdrio_clk_69; wire sdrio_clk_70; (* no_retiming = "true" *) reg regs0 = 1'd0; (* no_retiming = "true" *) reg regs1 = 1'd0; wire sdrio_clk_71; wire sdrio_clk_72; wire sdrio_clk_73; wire sdrio_clk_74; wire sdrio_clk_75; wire sdrio_clk_76; wire sdrio_clk_77; wire sdrio_clk_78; wire sdrio_clk_79; wire sdrio_clk_80; wire sdrio_clk_81; wire sdrio_clk_82; wire sdrio_clk_83; wire sdrio_clk_84; wire sdrio_clk_85; wire sdrio_clk_86; wire sdrio_clk_87; wire sdrio_clk_88; wire sdrio_clk_89; wire sdrio_clk_90; wire sdrio_clk_91; wire sdrio_clk_92; wire sdrio_clk_93; wire sdrio_clk_94; wire sdrio_clk_95; wire sdrio_clk_96; wire sdrio_clk_97; wire sdrio_clk_98; wire sdrio_clk_99; wire sdrio_clk_100; wire sdrio_clk_101; wire sdrio_clk_102; wire sdrio_clk_103; wire sdrio_clk_104; wire sdrio_clk_105; wire sdrio_clk_106; wire sdrio_clk_107; wire sdrio_clk_108; wire sdrio_clk_109; wire sdrio_clk_110; wire sdrio_clk_111; wire sdrio_clk_112; wire sdrio_clk_113; wire sdrio_clk_114; wire sdrio_clk_115; wire sdrio_clk_116; wire sdrio_clk_117; wire sdrio_clk_118; assign libresocsim_libresoc_reset = libresocsim_reset; always @(*) begin eint_tmp <= 3'd0; eint_tmp[0] <= libresocsim_libresoc_constraintmanager_eint_0; eint_tmp[1] <= libresocsim_libresoc_constraintmanager_eint_1; eint_tmp[2] <= libresocsim_libresoc_constraintmanager_eint_2; end assign libresocsim_libresoc_jtag_tck = jtag_tck; assign libresocsim_libresoc_jtag_tms = jtag_tms; assign libresocsim_libresoc_jtag_tdi = jtag_tdi; assign jtag_tdo = libresocsim_libresoc_jtag_tdo; assign nc_1 = nc; assign libresocsim_bus_error = libresocsim_error; always @(*) begin libresocsim_libresoc_interrupt <= 16'd0; libresocsim_libresoc_interrupt[13] <= eint_tmp[0]; libresocsim_libresoc_interrupt[14] <= eint_tmp[1]; libresocsim_libresoc_interrupt[15] <= eint_tmp[2]; libresocsim_libresoc_interrupt[0] <= libresocsim_irq; libresocsim_libresoc_interrupt[1] <= irq; end assign libresocsim_converter0_reset = (~libresocsim_libresoc_ibus_cyc); always @(*) begin libresocsim_interface0_converted_interface_dat_w <= 32'd0; case (libresocsim_converter0_counter) 1'd0: begin libresocsim_interface0_converted_interface_dat_w <= libresocsim_libresoc_ibus_dat_w[63:0]; end 1'd1: begin libresocsim_interface0_converted_interface_dat_w <= libresocsim_libresoc_ibus_dat_w[63:32]; end endcase end assign libresocsim_libresoc_ibus_dat_r = {libresocsim_interface0_converted_interface_dat_r, libresocsim_converter0_dat_r[63:32]}; always @(*) begin libresocsim_interface0_converted_interface_sel <= 4'd0; libresocsim_interface0_converted_interface_cyc <= 1'd0; libresocsim_libresoc_ibus_ack <= 1'd0; libresocsim_interface0_converted_interface_stb <= 1'd0; subfragments_converter0_next_state <= 1'd0; libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0; libresocsim_interface0_converted_interface_we <= 1'd0; libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd0; libresocsim_converter0_skip <= 1'd0; libresocsim_interface0_converted_interface_adr <= 30'd0; subfragments_converter0_next_state <= subfragments_converter0_state; case (subfragments_converter0_state) 1'd1: begin libresocsim_interface0_converted_interface_adr <= {libresocsim_libresoc_ibus_adr, libresocsim_converter0_counter}; case (libresocsim_converter0_counter) 1'd0: begin libresocsim_interface0_converted_interface_sel <= libresocsim_libresoc_ibus_sel[7:0]; end 1'd1: begin libresocsim_interface0_converted_interface_sel <= libresocsim_libresoc_ibus_sel[7:4]; end endcase if ((libresocsim_libresoc_ibus_stb & libresocsim_libresoc_ibus_cyc)) begin libresocsim_converter0_skip <= (libresocsim_interface0_converted_interface_sel == 1'd0); libresocsim_interface0_converted_interface_we <= libresocsim_libresoc_ibus_we; libresocsim_interface0_converted_interface_cyc <= (~libresocsim_converter0_skip); libresocsim_interface0_converted_interface_stb <= (~libresocsim_converter0_skip); if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin libresocsim_converter0_counter_subfragments_converter0_next_value <= (libresocsim_converter0_counter + 1'd1); libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1; if ((libresocsim_converter0_counter == 1'd1)) begin libresocsim_libresoc_ibus_ack <= 1'd1; subfragments_converter0_next_state <= 1'd0; end end end end default: begin libresocsim_converter0_counter_subfragments_converter0_next_value <= 1'd0; libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= 1'd1; if ((libresocsim_libresoc_ibus_stb & libresocsim_libresoc_ibus_cyc)) begin subfragments_converter0_next_state <= 1'd1; end end endcase end assign libresocsim_converter1_reset = (~libresocsim_libresoc_dbus_cyc); always @(*) begin libresocsim_interface1_converted_interface_dat_w <= 32'd0; case (libresocsim_converter1_counter) 1'd0: begin libresocsim_interface1_converted_interface_dat_w <= libresocsim_libresoc_dbus_dat_w[63:0]; end 1'd1: begin libresocsim_interface1_converted_interface_dat_w <= libresocsim_libresoc_dbus_dat_w[63:32]; end endcase end assign libresocsim_libresoc_dbus_dat_r = {libresocsim_interface1_converted_interface_dat_r, libresocsim_converter1_dat_r[63:32]}; always @(*) begin libresocsim_interface1_converted_interface_we <= 1'd0; subfragments_converter1_next_state <= 1'd0; libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0; libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd0; libresocsim_converter1_skip <= 1'd0; libresocsim_libresoc_dbus_ack <= 1'd0; libresocsim_interface1_converted_interface_adr <= 30'd0; libresocsim_interface1_converted_interface_sel <= 4'd0; libresocsim_interface1_converted_interface_cyc <= 1'd0; libresocsim_interface1_converted_interface_stb <= 1'd0; subfragments_converter1_next_state <= subfragments_converter1_state; case (subfragments_converter1_state) 1'd1: begin libresocsim_interface1_converted_interface_adr <= {libresocsim_libresoc_dbus_adr, libresocsim_converter1_counter}; case (libresocsim_converter1_counter) 1'd0: begin libresocsim_interface1_converted_interface_sel <= libresocsim_libresoc_dbus_sel[7:0]; end 1'd1: begin libresocsim_interface1_converted_interface_sel <= libresocsim_libresoc_dbus_sel[7:4]; end endcase if ((libresocsim_libresoc_dbus_stb & libresocsim_libresoc_dbus_cyc)) begin libresocsim_converter1_skip <= (libresocsim_interface1_converted_interface_sel == 1'd0); libresocsim_interface1_converted_interface_we <= libresocsim_libresoc_dbus_we; libresocsim_interface1_converted_interface_cyc <= (~libresocsim_converter1_skip); libresocsim_interface1_converted_interface_stb <= (~libresocsim_converter1_skip); if ((libresocsim_interface1_converted_interface_ack | libresocsim_converter1_skip)) begin libresocsim_converter1_counter_subfragments_converter1_next_value <= (libresocsim_converter1_counter + 1'd1); libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1; if ((libresocsim_converter1_counter == 1'd1)) begin libresocsim_libresoc_dbus_ack <= 1'd1; subfragments_converter1_next_state <= 1'd0; end end end end default: begin libresocsim_converter1_counter_subfragments_converter1_next_value <= 1'd0; libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= 1'd1; if ((libresocsim_libresoc_dbus_stb & libresocsim_libresoc_dbus_cyc)) begin subfragments_converter1_next_state <= 1'd1; end end endcase end assign libresocsim_reset = libresocsim_reset_re; assign libresocsim_bus_errors_status = libresocsim_bus_errors; always @(*) begin libresocsim_we <= 4'd0; libresocsim_we[0] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[0]); libresocsim_we[1] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[1]); libresocsim_we[2] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[2]); libresocsim_we[3] <= (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & libresocsim_ram_bus_we) & libresocsim_ram_bus_sel[3]); end assign libresocsim_adr = libresocsim_ram_bus_adr[6:0]; assign libresocsim_ram_bus_dat_r = libresocsim_dat_r; assign libresocsim_dat_w = libresocsim_ram_bus_dat_w; assign libresocsim_zero_trigger = (libresocsim_value != 1'd0); assign libresocsim_eventmanager_status_w = libresocsim_zero_status; always @(*) begin libresocsim_zero_clear <= 1'd0; if ((libresocsim_eventmanager_pending_re & libresocsim_eventmanager_pending_r)) begin libresocsim_zero_clear <= 1'd1; end end assign libresocsim_eventmanager_pending_w = libresocsim_zero_pending; assign libresocsim_irq = (libresocsim_eventmanager_pending_w & libresocsim_eventmanager_storage); assign libresocsim_zero_status = libresocsim_zero_trigger; always @(*) begin ram_we <= 4'd0; ram_we[0] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[0]); ram_we[1] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[1]); ram_we[2] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[2]); ram_we[3] <= (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & ram_bus_ram_bus_we) & ram_bus_ram_bus_sel[3]); end assign ram_adr = ram_bus_ram_bus_adr[4:0]; assign ram_bus_ram_bus_dat_r = ram_dat_r; assign ram_dat_w = ram_bus_ram_bus_dat_w; assign sys_clk_1 = sys_clk; assign por_clk = sys_clk; assign sys_rst_1 = int_rst; assign dfi_p0_address = sdram_master_p0_address; assign dfi_p0_bank = sdram_master_p0_bank; assign dfi_p0_cas_n = sdram_master_p0_cas_n; assign dfi_p0_cs_n = sdram_master_p0_cs_n; assign dfi_p0_ras_n = sdram_master_p0_ras_n; assign dfi_p0_we_n = sdram_master_p0_we_n; assign dfi_p0_cke = sdram_master_p0_cke; assign dfi_p0_odt = sdram_master_p0_odt; assign dfi_p0_reset_n = sdram_master_p0_reset_n; assign dfi_p0_act_n = sdram_master_p0_act_n; assign dfi_p0_wrdata = sdram_master_p0_wrdata; assign dfi_p0_wrdata_en = sdram_master_p0_wrdata_en; assign dfi_p0_wrdata_mask = sdram_master_p0_wrdata_mask; assign dfi_p0_rddata_en = sdram_master_p0_rddata_en; assign sdram_master_p0_rddata = dfi_p0_rddata; assign sdram_master_p0_rddata_valid = dfi_p0_rddata_valid; assign sdram_slave_p0_address = sdram_dfi_p0_address; assign sdram_slave_p0_bank = sdram_dfi_p0_bank; assign sdram_slave_p0_cas_n = sdram_dfi_p0_cas_n; assign sdram_slave_p0_cs_n = sdram_dfi_p0_cs_n; assign sdram_slave_p0_ras_n = sdram_dfi_p0_ras_n; assign sdram_slave_p0_we_n = sdram_dfi_p0_we_n; assign sdram_slave_p0_cke = sdram_dfi_p0_cke; assign sdram_slave_p0_odt = sdram_dfi_p0_odt; assign sdram_slave_p0_reset_n = sdram_dfi_p0_reset_n; assign sdram_slave_p0_act_n = sdram_dfi_p0_act_n; assign sdram_slave_p0_wrdata = sdram_dfi_p0_wrdata; assign sdram_slave_p0_wrdata_en = sdram_dfi_p0_wrdata_en; assign sdram_slave_p0_wrdata_mask = sdram_dfi_p0_wrdata_mask; assign sdram_slave_p0_rddata_en = sdram_dfi_p0_rddata_en; assign sdram_dfi_p0_rddata = sdram_slave_p0_rddata; assign sdram_dfi_p0_rddata_valid = sdram_slave_p0_rddata_valid; always @(*) begin sdram_master_p0_ras_n <= 1'd1; sdram_master_p0_we_n <= 1'd1; sdram_master_p0_cke <= 1'd0; sdram_master_p0_odt <= 1'd0; sdram_master_p0_reset_n <= 1'd0; sdram_master_p0_act_n <= 1'd1; sdram_inti_p0_rddata <= 16'd0; sdram_master_p0_wrdata <= 16'd0; sdram_inti_p0_rddata_valid <= 1'd0; sdram_master_p0_wrdata_en <= 1'd0; sdram_master_p0_wrdata_mask <= 2'd0; sdram_master_p0_rddata_en <= 1'd0; sdram_slave_p0_rddata <= 16'd0; sdram_slave_p0_rddata_valid <= 1'd0; sdram_master_p0_address <= 13'd0; sdram_master_p0_bank <= 2'd0; sdram_master_p0_cas_n <= 1'd1; sdram_master_p0_cs_n <= 1'd1; if (sdram_sel) begin sdram_master_p0_address <= sdram_slave_p0_address; sdram_master_p0_bank <= sdram_slave_p0_bank; sdram_master_p0_cas_n <= sdram_slave_p0_cas_n; sdram_master_p0_cs_n <= sdram_slave_p0_cs_n; sdram_master_p0_ras_n <= sdram_slave_p0_ras_n; sdram_master_p0_we_n <= sdram_slave_p0_we_n; sdram_master_p0_cke <= sdram_slave_p0_cke; sdram_master_p0_odt <= sdram_slave_p0_odt; sdram_master_p0_reset_n <= sdram_slave_p0_reset_n; sdram_master_p0_act_n <= sdram_slave_p0_act_n; sdram_master_p0_wrdata <= sdram_slave_p0_wrdata; sdram_master_p0_wrdata_en <= sdram_slave_p0_wrdata_en; sdram_master_p0_wrdata_mask <= sdram_slave_p0_wrdata_mask; sdram_master_p0_rddata_en <= sdram_slave_p0_rddata_en; sdram_slave_p0_rddata <= sdram_master_p0_rddata; sdram_slave_p0_rddata_valid <= sdram_master_p0_rddata_valid; end else begin sdram_master_p0_address <= sdram_inti_p0_address; sdram_master_p0_bank <= sdram_inti_p0_bank; sdram_master_p0_cas_n <= sdram_inti_p0_cas_n; sdram_master_p0_cs_n <= sdram_inti_p0_cs_n; sdram_master_p0_ras_n <= sdram_inti_p0_ras_n; sdram_master_p0_we_n <= sdram_inti_p0_we_n; sdram_master_p0_cke <= sdram_inti_p0_cke; sdram_master_p0_odt <= sdram_inti_p0_odt; sdram_master_p0_reset_n <= sdram_inti_p0_reset_n; sdram_master_p0_act_n <= sdram_inti_p0_act_n; sdram_master_p0_wrdata <= sdram_inti_p0_wrdata; sdram_master_p0_wrdata_en <= sdram_inti_p0_wrdata_en; sdram_master_p0_wrdata_mask <= sdram_inti_p0_wrdata_mask; sdram_master_p0_rddata_en <= sdram_inti_p0_rddata_en; sdram_inti_p0_rddata <= sdram_master_p0_rddata; sdram_inti_p0_rddata_valid <= sdram_master_p0_rddata_valid; end end assign sdram_inti_p0_cke = sdram_cke_1; assign sdram_inti_p0_odt = sdram_odt; assign sdram_inti_p0_reset_n = sdram_reset_n; always @(*) begin sdram_inti_p0_we_n <= 1'd1; sdram_inti_p0_cas_n <= 1'd1; sdram_inti_p0_cs_n <= 1'd1; sdram_inti_p0_ras_n <= 1'd1; if (sdram_command_issue_re) begin sdram_inti_p0_cs_n <= {1{(~sdram_command_storage[0])}}; sdram_inti_p0_we_n <= (~sdram_command_storage[1]); sdram_inti_p0_cas_n <= (~sdram_command_storage[2]); sdram_inti_p0_ras_n <= (~sdram_command_storage[3]); end else begin sdram_inti_p0_cs_n <= {1{1'd1}}; sdram_inti_p0_we_n <= 1'd1; sdram_inti_p0_cas_n <= 1'd1; sdram_inti_p0_ras_n <= 1'd1; end end assign sdram_inti_p0_address = sdram_address_storage; assign sdram_inti_p0_bank = sdram_baddress_storage; assign sdram_inti_p0_wrdata_en = (sdram_command_issue_re & sdram_command_storage[4]); assign sdram_inti_p0_rddata_en = (sdram_command_issue_re & sdram_command_storage[5]); assign sdram_inti_p0_wrdata = sdram_wrdata_storage; assign sdram_inti_p0_wrdata_mask = 1'd0; assign sdram_bankmachine0_req_valid = sdram_interface_bank0_valid; assign sdram_interface_bank0_ready = sdram_bankmachine0_req_ready; assign sdram_bankmachine0_req_we = sdram_interface_bank0_we; assign sdram_bankmachine0_req_addr = sdram_interface_bank0_addr; assign sdram_interface_bank0_lock = sdram_bankmachine0_req_lock; assign sdram_interface_bank0_wdata_ready = sdram_bankmachine0_req_wdata_ready; assign sdram_interface_bank0_rdata_valid = sdram_bankmachine0_req_rdata_valid; assign sdram_bankmachine1_req_valid = sdram_interface_bank1_valid; assign sdram_interface_bank1_ready = sdram_bankmachine1_req_ready; assign sdram_bankmachine1_req_we = sdram_interface_bank1_we; assign sdram_bankmachine1_req_addr = sdram_interface_bank1_addr; assign sdram_interface_bank1_lock = sdram_bankmachine1_req_lock; assign sdram_interface_bank1_wdata_ready = sdram_bankmachine1_req_wdata_ready; assign sdram_interface_bank1_rdata_valid = sdram_bankmachine1_req_rdata_valid; assign sdram_bankmachine2_req_valid = sdram_interface_bank2_valid; assign sdram_interface_bank2_ready = sdram_bankmachine2_req_ready; assign sdram_bankmachine2_req_we = sdram_interface_bank2_we; assign sdram_bankmachine2_req_addr = sdram_interface_bank2_addr; assign sdram_interface_bank2_lock = sdram_bankmachine2_req_lock; assign sdram_interface_bank2_wdata_ready = sdram_bankmachine2_req_wdata_ready; assign sdram_interface_bank2_rdata_valid = sdram_bankmachine2_req_rdata_valid; assign sdram_bankmachine3_req_valid = sdram_interface_bank3_valid; assign sdram_interface_bank3_ready = sdram_bankmachine3_req_ready; assign sdram_bankmachine3_req_we = sdram_interface_bank3_we; assign sdram_bankmachine3_req_addr = sdram_interface_bank3_addr; assign sdram_interface_bank3_lock = sdram_bankmachine3_req_lock; assign sdram_interface_bank3_wdata_ready = sdram_bankmachine3_req_wdata_ready; assign sdram_interface_bank3_rdata_valid = sdram_bankmachine3_req_rdata_valid; assign sdram_timer_wait = (~sdram_timer_done0); assign sdram_postponer_req_i = sdram_timer_done0; assign sdram_wants_refresh = sdram_postponer_req_o; assign sdram_timer_done1 = (sdram_timer_count1 == 1'd0); assign sdram_timer_done0 = sdram_timer_done1; assign sdram_timer_count0 = sdram_timer_count1; assign sdram_sequencer_start1 = (sdram_sequencer_start0 | (sdram_sequencer_count != 1'd0)); assign sdram_sequencer_done0 = (sdram_sequencer_done1 & (sdram_sequencer_count == 1'd0)); always @(*) begin sdram_sequencer_start0 <= 1'd0; subfragments_refresher_next_state <= 2'd0; sdram_cmd_valid <= 1'd0; sdram_cmd_last <= 1'd0; subfragments_refresher_next_state <= subfragments_refresher_state; case (subfragments_refresher_state) 1'd1: begin sdram_cmd_valid <= 1'd1; if (sdram_cmd_ready) begin sdram_sequencer_start0 <= 1'd1; subfragments_refresher_next_state <= 2'd2; end end 2'd2: begin sdram_cmd_valid <= 1'd1; if (sdram_sequencer_done0) begin sdram_cmd_valid <= 1'd0; sdram_cmd_last <= 1'd1; subfragments_refresher_next_state <= 1'd0; end end default: begin if (1'd1) begin if (sdram_wants_refresh) begin subfragments_refresher_next_state <= 1'd1; end end end endcase end assign sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = sdram_bankmachine0_req_valid; assign sdram_bankmachine0_req_ready = sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine0_req_we; assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine0_req_addr; assign sdram_bankmachine0_cmd_buffer_sink_valid = sdram_bankmachine0_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine0_cmd_buffer_lookahead_source_ready = sdram_bankmachine0_cmd_buffer_sink_ready; assign sdram_bankmachine0_cmd_buffer_sink_first = sdram_bankmachine0_cmd_buffer_lookahead_source_first; assign sdram_bankmachine0_cmd_buffer_sink_last = sdram_bankmachine0_cmd_buffer_lookahead_source_last; assign sdram_bankmachine0_cmd_buffer_sink_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine0_cmd_buffer_sink_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine0_cmd_buffer_source_ready = (sdram_bankmachine0_req_wdata_ready | sdram_bankmachine0_req_rdata_valid); assign sdram_bankmachine0_req_lock = (sdram_bankmachine0_cmd_buffer_lookahead_source_valid | sdram_bankmachine0_cmd_buffer_source_valid); assign sdram_bankmachine0_row_hit = (sdram_bankmachine0_row == sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]); assign sdram_bankmachine0_cmd_payload_ba = 1'd0; always @(*) begin sdram_bankmachine0_cmd_payload_a <= 13'd0; if (sdram_bankmachine0_row_col_n_addr_sel) begin sdram_bankmachine0_cmd_payload_a <= sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]; end else begin sdram_bankmachine0_cmd_payload_a <= ((sdram_bankmachine0_auto_precharge <<< 4'd10) | {sdram_bankmachine0_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}}); end end assign sdram_bankmachine0_twtpcon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_cmd_payload_is_write); assign sdram_bankmachine0_trccon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open); assign sdram_bankmachine0_trascon_valid = ((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_ready) & sdram_bankmachine0_row_open); always @(*) begin sdram_bankmachine0_auto_precharge <= 1'd0; if ((sdram_bankmachine0_cmd_buffer_lookahead_source_valid & sdram_bankmachine0_cmd_buffer_source_valid)) begin if ((sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9])) begin sdram_bankmachine0_auto_precharge <= (sdram_bankmachine0_row_close == 1'd0); end end end assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; assign sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine0_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine0_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine0_cmd_buffer_lookahead_source_valid = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; assign sdram_bankmachine0_cmd_buffer_lookahead_source_first = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine0_cmd_buffer_lookahead_source_last = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = sdram_bankmachine0_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine0_cmd_buffer_lookahead_replace) begin sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine0_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | sdram_bankmachine0_cmd_buffer_lookahead_replace)); assign sdram_bankmachine0_cmd_buffer_lookahead_do_read = (sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine0_cmd_buffer_lookahead_consume; assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine0_cmd_buffer_sink_ready = ((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine0_cmd_payload_cas <= 1'd0; sdram_bankmachine0_cmd_payload_ras <= 1'd0; sdram_bankmachine0_cmd_payload_we <= 1'd0; sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine0_cmd_payload_is_read <= 1'd0; sdram_bankmachine0_cmd_payload_is_write <= 1'd0; sdram_bankmachine0_req_wdata_ready <= 1'd0; sdram_bankmachine0_req_rdata_valid <= 1'd0; sdram_bankmachine0_refresh_gnt <= 1'd0; subfragments_bankmachine0_next_state <= 3'd0; sdram_bankmachine0_cmd_valid <= 1'd0; sdram_bankmachine0_row_open <= 1'd0; sdram_bankmachine0_row_close <= 1'd0; subfragments_bankmachine0_next_state <= subfragments_bankmachine0_state; case (subfragments_bankmachine0_state) 1'd1: begin if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin sdram_bankmachine0_cmd_valid <= 1'd1; if (sdram_bankmachine0_cmd_ready) begin subfragments_bankmachine0_next_state <= 3'd5; end sdram_bankmachine0_cmd_payload_ras <= 1'd1; sdram_bankmachine0_cmd_payload_we <= 1'd1; sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine0_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine0_twtpcon_ready & sdram_bankmachine0_trascon_ready)) begin subfragments_bankmachine0_next_state <= 3'd5; end sdram_bankmachine0_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine0_trccon_ready) begin sdram_bankmachine0_row_col_n_addr_sel <= 1'd1; sdram_bankmachine0_row_open <= 1'd1; sdram_bankmachine0_cmd_valid <= 1'd1; sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine0_cmd_ready) begin subfragments_bankmachine0_next_state <= 3'd6; end sdram_bankmachine0_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine0_twtpcon_ready) begin sdram_bankmachine0_refresh_gnt <= 1'd1; end sdram_bankmachine0_row_close <= 1'd1; sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine0_refresh_req)) begin subfragments_bankmachine0_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine0_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine0_next_state <= 1'd0; end default: begin if (sdram_bankmachine0_refresh_req) begin subfragments_bankmachine0_next_state <= 3'd4; end else begin if (sdram_bankmachine0_cmd_buffer_source_valid) begin if (sdram_bankmachine0_row_opened) begin if (sdram_bankmachine0_row_hit) begin sdram_bankmachine0_cmd_valid <= 1'd1; if (sdram_bankmachine0_cmd_buffer_source_payload_we) begin sdram_bankmachine0_req_wdata_ready <= sdram_bankmachine0_cmd_ready; sdram_bankmachine0_cmd_payload_is_write <= 1'd1; sdram_bankmachine0_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine0_req_rdata_valid <= sdram_bankmachine0_cmd_ready; sdram_bankmachine0_cmd_payload_is_read <= 1'd1; end sdram_bankmachine0_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine0_cmd_ready & sdram_bankmachine0_auto_precharge)) begin subfragments_bankmachine0_next_state <= 2'd2; end end else begin subfragments_bankmachine0_next_state <= 1'd1; end end else begin subfragments_bankmachine0_next_state <= 2'd3; end end end end endcase end assign sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = sdram_bankmachine1_req_valid; assign sdram_bankmachine1_req_ready = sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine1_req_we; assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine1_req_addr; assign sdram_bankmachine1_cmd_buffer_sink_valid = sdram_bankmachine1_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine1_cmd_buffer_lookahead_source_ready = sdram_bankmachine1_cmd_buffer_sink_ready; assign sdram_bankmachine1_cmd_buffer_sink_first = sdram_bankmachine1_cmd_buffer_lookahead_source_first; assign sdram_bankmachine1_cmd_buffer_sink_last = sdram_bankmachine1_cmd_buffer_lookahead_source_last; assign sdram_bankmachine1_cmd_buffer_sink_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine1_cmd_buffer_sink_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine1_cmd_buffer_source_ready = (sdram_bankmachine1_req_wdata_ready | sdram_bankmachine1_req_rdata_valid); assign sdram_bankmachine1_req_lock = (sdram_bankmachine1_cmd_buffer_lookahead_source_valid | sdram_bankmachine1_cmd_buffer_source_valid); assign sdram_bankmachine1_row_hit = (sdram_bankmachine1_row == sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]); assign sdram_bankmachine1_cmd_payload_ba = 1'd1; always @(*) begin sdram_bankmachine1_cmd_payload_a <= 13'd0; if (sdram_bankmachine1_row_col_n_addr_sel) begin sdram_bankmachine1_cmd_payload_a <= sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]; end else begin sdram_bankmachine1_cmd_payload_a <= ((sdram_bankmachine1_auto_precharge <<< 4'd10) | {sdram_bankmachine1_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}}); end end assign sdram_bankmachine1_twtpcon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_cmd_payload_is_write); assign sdram_bankmachine1_trccon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open); assign sdram_bankmachine1_trascon_valid = ((sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_ready) & sdram_bankmachine1_row_open); always @(*) begin sdram_bankmachine1_auto_precharge <= 1'd0; if ((sdram_bankmachine1_cmd_buffer_lookahead_source_valid & sdram_bankmachine1_cmd_buffer_source_valid)) begin if ((sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9])) begin sdram_bankmachine1_auto_precharge <= (sdram_bankmachine1_row_close == 1'd0); end end end assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; assign sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine1_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine1_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine1_cmd_buffer_lookahead_source_valid = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; assign sdram_bankmachine1_cmd_buffer_lookahead_source_first = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine1_cmd_buffer_lookahead_source_last = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = sdram_bankmachine1_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine1_cmd_buffer_lookahead_replace) begin sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine1_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | sdram_bankmachine1_cmd_buffer_lookahead_replace)); assign sdram_bankmachine1_cmd_buffer_lookahead_do_read = (sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine1_cmd_buffer_lookahead_consume; assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine1_cmd_buffer_sink_ready = ((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine1_row_open <= 1'd0; sdram_bankmachine1_row_close <= 1'd0; sdram_bankmachine1_cmd_payload_cas <= 1'd0; sdram_bankmachine1_cmd_payload_ras <= 1'd0; sdram_bankmachine1_cmd_payload_we <= 1'd0; sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; subfragments_bankmachine1_next_state <= 3'd0; sdram_bankmachine1_cmd_payload_is_read <= 1'd0; sdram_bankmachine1_cmd_payload_is_write <= 1'd0; sdram_bankmachine1_req_wdata_ready <= 1'd0; sdram_bankmachine1_req_rdata_valid <= 1'd0; sdram_bankmachine1_refresh_gnt <= 1'd0; sdram_bankmachine1_cmd_valid <= 1'd0; subfragments_bankmachine1_next_state <= subfragments_bankmachine1_state; case (subfragments_bankmachine1_state) 1'd1: begin if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin sdram_bankmachine1_cmd_valid <= 1'd1; if (sdram_bankmachine1_cmd_ready) begin subfragments_bankmachine1_next_state <= 3'd5; end sdram_bankmachine1_cmd_payload_ras <= 1'd1; sdram_bankmachine1_cmd_payload_we <= 1'd1; sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine1_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine1_twtpcon_ready & sdram_bankmachine1_trascon_ready)) begin subfragments_bankmachine1_next_state <= 3'd5; end sdram_bankmachine1_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine1_trccon_ready) begin sdram_bankmachine1_row_col_n_addr_sel <= 1'd1; sdram_bankmachine1_row_open <= 1'd1; sdram_bankmachine1_cmd_valid <= 1'd1; sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine1_cmd_ready) begin subfragments_bankmachine1_next_state <= 3'd6; end sdram_bankmachine1_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine1_twtpcon_ready) begin sdram_bankmachine1_refresh_gnt <= 1'd1; end sdram_bankmachine1_row_close <= 1'd1; sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine1_refresh_req)) begin subfragments_bankmachine1_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine1_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine1_next_state <= 1'd0; end default: begin if (sdram_bankmachine1_refresh_req) begin subfragments_bankmachine1_next_state <= 3'd4; end else begin if (sdram_bankmachine1_cmd_buffer_source_valid) begin if (sdram_bankmachine1_row_opened) begin if (sdram_bankmachine1_row_hit) begin sdram_bankmachine1_cmd_valid <= 1'd1; if (sdram_bankmachine1_cmd_buffer_source_payload_we) begin sdram_bankmachine1_req_wdata_ready <= sdram_bankmachine1_cmd_ready; sdram_bankmachine1_cmd_payload_is_write <= 1'd1; sdram_bankmachine1_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine1_req_rdata_valid <= sdram_bankmachine1_cmd_ready; sdram_bankmachine1_cmd_payload_is_read <= 1'd1; end sdram_bankmachine1_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine1_cmd_ready & sdram_bankmachine1_auto_precharge)) begin subfragments_bankmachine1_next_state <= 2'd2; end end else begin subfragments_bankmachine1_next_state <= 1'd1; end end else begin subfragments_bankmachine1_next_state <= 2'd3; end end end end endcase end assign sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = sdram_bankmachine2_req_valid; assign sdram_bankmachine2_req_ready = sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine2_req_we; assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine2_req_addr; assign sdram_bankmachine2_cmd_buffer_sink_valid = sdram_bankmachine2_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine2_cmd_buffer_lookahead_source_ready = sdram_bankmachine2_cmd_buffer_sink_ready; assign sdram_bankmachine2_cmd_buffer_sink_first = sdram_bankmachine2_cmd_buffer_lookahead_source_first; assign sdram_bankmachine2_cmd_buffer_sink_last = sdram_bankmachine2_cmd_buffer_lookahead_source_last; assign sdram_bankmachine2_cmd_buffer_sink_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine2_cmd_buffer_sink_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine2_cmd_buffer_source_ready = (sdram_bankmachine2_req_wdata_ready | sdram_bankmachine2_req_rdata_valid); assign sdram_bankmachine2_req_lock = (sdram_bankmachine2_cmd_buffer_lookahead_source_valid | sdram_bankmachine2_cmd_buffer_source_valid); assign sdram_bankmachine2_row_hit = (sdram_bankmachine2_row == sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]); assign sdram_bankmachine2_cmd_payload_ba = 2'd2; always @(*) begin sdram_bankmachine2_cmd_payload_a <= 13'd0; if (sdram_bankmachine2_row_col_n_addr_sel) begin sdram_bankmachine2_cmd_payload_a <= sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]; end else begin sdram_bankmachine2_cmd_payload_a <= ((sdram_bankmachine2_auto_precharge <<< 4'd10) | {sdram_bankmachine2_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}}); end end assign sdram_bankmachine2_twtpcon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_cmd_payload_is_write); assign sdram_bankmachine2_trccon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open); assign sdram_bankmachine2_trascon_valid = ((sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_ready) & sdram_bankmachine2_row_open); always @(*) begin sdram_bankmachine2_auto_precharge <= 1'd0; if ((sdram_bankmachine2_cmd_buffer_lookahead_source_valid & sdram_bankmachine2_cmd_buffer_source_valid)) begin if ((sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9])) begin sdram_bankmachine2_auto_precharge <= (sdram_bankmachine2_row_close == 1'd0); end end end assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; assign sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine2_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine2_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine2_cmd_buffer_lookahead_source_valid = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; assign sdram_bankmachine2_cmd_buffer_lookahead_source_first = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine2_cmd_buffer_lookahead_source_last = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = sdram_bankmachine2_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine2_cmd_buffer_lookahead_replace) begin sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine2_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | sdram_bankmachine2_cmd_buffer_lookahead_replace)); assign sdram_bankmachine2_cmd_buffer_lookahead_do_read = (sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine2_cmd_buffer_lookahead_consume; assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine2_cmd_buffer_sink_ready = ((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine2_refresh_gnt <= 1'd0; sdram_bankmachine2_cmd_valid <= 1'd0; subfragments_bankmachine2_next_state <= 3'd0; sdram_bankmachine2_row_open <= 1'd0; sdram_bankmachine2_row_close <= 1'd0; sdram_bankmachine2_cmd_payload_cas <= 1'd0; sdram_bankmachine2_cmd_payload_ras <= 1'd0; sdram_bankmachine2_cmd_payload_we <= 1'd0; sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; sdram_bankmachine2_cmd_payload_is_read <= 1'd0; sdram_bankmachine2_cmd_payload_is_write <= 1'd0; sdram_bankmachine2_req_wdata_ready <= 1'd0; sdram_bankmachine2_req_rdata_valid <= 1'd0; subfragments_bankmachine2_next_state <= subfragments_bankmachine2_state; case (subfragments_bankmachine2_state) 1'd1: begin if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin sdram_bankmachine2_cmd_valid <= 1'd1; if (sdram_bankmachine2_cmd_ready) begin subfragments_bankmachine2_next_state <= 3'd5; end sdram_bankmachine2_cmd_payload_ras <= 1'd1; sdram_bankmachine2_cmd_payload_we <= 1'd1; sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine2_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine2_twtpcon_ready & sdram_bankmachine2_trascon_ready)) begin subfragments_bankmachine2_next_state <= 3'd5; end sdram_bankmachine2_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine2_trccon_ready) begin sdram_bankmachine2_row_col_n_addr_sel <= 1'd1; sdram_bankmachine2_row_open <= 1'd1; sdram_bankmachine2_cmd_valid <= 1'd1; sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine2_cmd_ready) begin subfragments_bankmachine2_next_state <= 3'd6; end sdram_bankmachine2_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine2_twtpcon_ready) begin sdram_bankmachine2_refresh_gnt <= 1'd1; end sdram_bankmachine2_row_close <= 1'd1; sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine2_refresh_req)) begin subfragments_bankmachine2_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine2_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine2_next_state <= 1'd0; end default: begin if (sdram_bankmachine2_refresh_req) begin subfragments_bankmachine2_next_state <= 3'd4; end else begin if (sdram_bankmachine2_cmd_buffer_source_valid) begin if (sdram_bankmachine2_row_opened) begin if (sdram_bankmachine2_row_hit) begin sdram_bankmachine2_cmd_valid <= 1'd1; if (sdram_bankmachine2_cmd_buffer_source_payload_we) begin sdram_bankmachine2_req_wdata_ready <= sdram_bankmachine2_cmd_ready; sdram_bankmachine2_cmd_payload_is_write <= 1'd1; sdram_bankmachine2_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine2_req_rdata_valid <= sdram_bankmachine2_cmd_ready; sdram_bankmachine2_cmd_payload_is_read <= 1'd1; end sdram_bankmachine2_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine2_cmd_ready & sdram_bankmachine2_auto_precharge)) begin subfragments_bankmachine2_next_state <= 2'd2; end end else begin subfragments_bankmachine2_next_state <= 1'd1; end end else begin subfragments_bankmachine2_next_state <= 2'd3; end end end end endcase end assign sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = sdram_bankmachine3_req_valid; assign sdram_bankmachine3_req_ready = sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine3_req_we; assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine3_req_addr; assign sdram_bankmachine3_cmd_buffer_sink_valid = sdram_bankmachine3_cmd_buffer_lookahead_source_valid; assign sdram_bankmachine3_cmd_buffer_lookahead_source_ready = sdram_bankmachine3_cmd_buffer_sink_ready; assign sdram_bankmachine3_cmd_buffer_sink_first = sdram_bankmachine3_cmd_buffer_lookahead_source_first; assign sdram_bankmachine3_cmd_buffer_sink_last = sdram_bankmachine3_cmd_buffer_lookahead_source_last; assign sdram_bankmachine3_cmd_buffer_sink_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; assign sdram_bankmachine3_cmd_buffer_sink_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; assign sdram_bankmachine3_cmd_buffer_source_ready = (sdram_bankmachine3_req_wdata_ready | sdram_bankmachine3_req_rdata_valid); assign sdram_bankmachine3_req_lock = (sdram_bankmachine3_cmd_buffer_lookahead_source_valid | sdram_bankmachine3_cmd_buffer_source_valid); assign sdram_bankmachine3_row_hit = (sdram_bankmachine3_row == sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]); assign sdram_bankmachine3_cmd_payload_ba = 2'd3; always @(*) begin sdram_bankmachine3_cmd_payload_a <= 13'd0; if (sdram_bankmachine3_row_col_n_addr_sel) begin sdram_bankmachine3_cmd_payload_a <= sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]; end else begin sdram_bankmachine3_cmd_payload_a <= ((sdram_bankmachine3_auto_precharge <<< 4'd10) | {sdram_bankmachine3_cmd_buffer_source_payload_addr[8:0], {0{1'd0}}}); end end assign sdram_bankmachine3_twtpcon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_cmd_payload_is_write); assign sdram_bankmachine3_trccon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open); assign sdram_bankmachine3_trascon_valid = ((sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_ready) & sdram_bankmachine3_row_open); always @(*) begin sdram_bankmachine3_auto_precharge <= 1'd0; if ((sdram_bankmachine3_cmd_buffer_lookahead_source_valid & sdram_bankmachine3_cmd_buffer_source_valid)) begin if ((sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:9] != sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9])) begin sdram_bankmachine3_auto_precharge <= (sdram_bankmachine3_row_close == 1'd0); end end end assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; assign {sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; assign sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine3_cmd_buffer_lookahead_sink_first; assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine3_cmd_buffer_lookahead_sink_last; assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; assign sdram_bankmachine3_cmd_buffer_lookahead_source_valid = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; assign sdram_bankmachine3_cmd_buffer_lookahead_source_first = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; assign sdram_bankmachine3_cmd_buffer_lookahead_source_last = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = sdram_bankmachine3_cmd_buffer_lookahead_source_ready; always @(*) begin sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0; if (sdram_bankmachine3_cmd_buffer_lookahead_replace) begin sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); end else begin sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= sdram_bankmachine3_cmd_buffer_lookahead_produce; end end assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | sdram_bankmachine3_cmd_buffer_lookahead_replace)); assign sdram_bankmachine3_cmd_buffer_lookahead_do_read = (sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine3_cmd_buffer_lookahead_consume; assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8); assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); assign sdram_bankmachine3_cmd_buffer_sink_ready = ((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready); always @(*) begin sdram_bankmachine3_cmd_payload_is_read <= 1'd0; sdram_bankmachine3_cmd_payload_is_write <= 1'd0; sdram_bankmachine3_req_wdata_ready <= 1'd0; sdram_bankmachine3_req_rdata_valid <= 1'd0; subfragments_bankmachine3_next_state <= 3'd0; sdram_bankmachine3_refresh_gnt <= 1'd0; sdram_bankmachine3_cmd_valid <= 1'd0; sdram_bankmachine3_row_open <= 1'd0; sdram_bankmachine3_row_close <= 1'd0; sdram_bankmachine3_cmd_payload_cas <= 1'd0; sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; sdram_bankmachine3_cmd_payload_ras <= 1'd0; sdram_bankmachine3_cmd_payload_we <= 1'd0; sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; subfragments_bankmachine3_next_state <= subfragments_bankmachine3_state; case (subfragments_bankmachine3_state) 1'd1: begin if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin sdram_bankmachine3_cmd_valid <= 1'd1; if (sdram_bankmachine3_cmd_ready) begin subfragments_bankmachine3_next_state <= 3'd5; end sdram_bankmachine3_cmd_payload_ras <= 1'd1; sdram_bankmachine3_cmd_payload_we <= 1'd1; sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; end sdram_bankmachine3_row_close <= 1'd1; end 2'd2: begin if ((sdram_bankmachine3_twtpcon_ready & sdram_bankmachine3_trascon_ready)) begin subfragments_bankmachine3_next_state <= 3'd5; end sdram_bankmachine3_row_close <= 1'd1; end 2'd3: begin if (sdram_bankmachine3_trccon_ready) begin sdram_bankmachine3_row_col_n_addr_sel <= 1'd1; sdram_bankmachine3_row_open <= 1'd1; sdram_bankmachine3_cmd_valid <= 1'd1; sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; if (sdram_bankmachine3_cmd_ready) begin subfragments_bankmachine3_next_state <= 3'd6; end sdram_bankmachine3_cmd_payload_ras <= 1'd1; end end 3'd4: begin if (sdram_bankmachine3_twtpcon_ready) begin sdram_bankmachine3_refresh_gnt <= 1'd1; end sdram_bankmachine3_row_close <= 1'd1; sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; if ((~sdram_bankmachine3_refresh_req)) begin subfragments_bankmachine3_next_state <= 1'd0; end end 3'd5: begin subfragments_bankmachine3_next_state <= 2'd3; end 3'd6: begin subfragments_bankmachine3_next_state <= 1'd0; end default: begin if (sdram_bankmachine3_refresh_req) begin subfragments_bankmachine3_next_state <= 3'd4; end else begin if (sdram_bankmachine3_cmd_buffer_source_valid) begin if (sdram_bankmachine3_row_opened) begin if (sdram_bankmachine3_row_hit) begin sdram_bankmachine3_cmd_valid <= 1'd1; if (sdram_bankmachine3_cmd_buffer_source_payload_we) begin sdram_bankmachine3_req_wdata_ready <= sdram_bankmachine3_cmd_ready; sdram_bankmachine3_cmd_payload_is_write <= 1'd1; sdram_bankmachine3_cmd_payload_we <= 1'd1; end else begin sdram_bankmachine3_req_rdata_valid <= sdram_bankmachine3_cmd_ready; sdram_bankmachine3_cmd_payload_is_read <= 1'd1; end sdram_bankmachine3_cmd_payload_cas <= 1'd1; if ((sdram_bankmachine3_cmd_ready & sdram_bankmachine3_auto_precharge)) begin subfragments_bankmachine3_next_state <= 2'd2; end end else begin subfragments_bankmachine3_next_state <= 1'd1; end end else begin subfragments_bankmachine3_next_state <= 2'd3; end end end end endcase end assign sdram_choose_req_want_cmds = 1'd1; assign sdram_trrdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & ((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))); assign sdram_tfawcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & ((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))); assign sdram_ras_allowed = (sdram_trrdcon_ready & sdram_tfawcon_ready); assign sdram_tccdcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_cmd_payload_is_write | sdram_choose_req_cmd_payload_is_read)); assign sdram_cas_allowed = sdram_tccdcon_ready; assign sdram_twtrcon_valid = ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); assign sdram_read_available = ((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_read) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_read)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_read)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_read)); assign sdram_write_available = ((((sdram_bankmachine0_cmd_valid & sdram_bankmachine0_cmd_payload_is_write) | (sdram_bankmachine1_cmd_valid & sdram_bankmachine1_cmd_payload_is_write)) | (sdram_bankmachine2_cmd_valid & sdram_bankmachine2_cmd_payload_is_write)) | (sdram_bankmachine3_cmd_valid & sdram_bankmachine3_cmd_payload_is_write)); assign sdram_max_time0 = (sdram_time0 == 1'd0); assign sdram_max_time1 = (sdram_time1 == 1'd0); assign sdram_bankmachine0_refresh_req = sdram_cmd_valid; assign sdram_bankmachine1_refresh_req = sdram_cmd_valid; assign sdram_bankmachine2_refresh_req = sdram_cmd_valid; assign sdram_bankmachine3_refresh_req = sdram_cmd_valid; assign sdram_go_to_refresh = (((sdram_bankmachine0_refresh_gnt & sdram_bankmachine1_refresh_gnt) & sdram_bankmachine2_refresh_gnt) & sdram_bankmachine3_refresh_gnt); assign sdram_interface_rdata = {sdram_dfi_p0_rddata}; assign {sdram_dfi_p0_wrdata} = sdram_interface_wdata; assign {sdram_dfi_p0_wrdata_mask} = (~sdram_interface_wdata_we); always @(*) begin sdram_choose_cmd_valids <= 4'd0; sdram_choose_cmd_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); sdram_choose_cmd_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); sdram_choose_cmd_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); sdram_choose_cmd_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_cmd_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_cmd_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_cmd_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_cmd_want_writes)))); end assign sdram_choose_cmd_request = sdram_choose_cmd_valids; assign sdram_choose_cmd_cmd_valid = rhs_array_muxed0; assign sdram_choose_cmd_cmd_payload_a = rhs_array_muxed1; assign sdram_choose_cmd_cmd_payload_ba = rhs_array_muxed2; assign sdram_choose_cmd_cmd_payload_is_read = rhs_array_muxed3; assign sdram_choose_cmd_cmd_payload_is_write = rhs_array_muxed4; assign sdram_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5; always @(*) begin sdram_choose_cmd_cmd_payload_cas <= 1'd0; if (sdram_choose_cmd_cmd_valid) begin sdram_choose_cmd_cmd_payload_cas <= t_array_muxed0; end end always @(*) begin sdram_choose_cmd_cmd_payload_ras <= 1'd0; if (sdram_choose_cmd_cmd_valid) begin sdram_choose_cmd_cmd_payload_ras <= t_array_muxed1; end end always @(*) begin sdram_choose_cmd_cmd_payload_we <= 1'd0; if (sdram_choose_cmd_cmd_valid) begin sdram_choose_cmd_cmd_payload_we <= t_array_muxed2; end end assign sdram_choose_cmd_ce = (sdram_choose_cmd_cmd_ready | (~sdram_choose_cmd_cmd_valid)); always @(*) begin sdram_choose_req_valids <= 4'd0; sdram_choose_req_valids[0] <= (sdram_bankmachine0_cmd_valid & (((sdram_bankmachine0_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine0_cmd_payload_ras & (~sdram_bankmachine0_cmd_payload_cas)) & (~sdram_bankmachine0_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine0_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine0_cmd_payload_is_write == sdram_choose_req_want_writes)))); sdram_choose_req_valids[1] <= (sdram_bankmachine1_cmd_valid & (((sdram_bankmachine1_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine1_cmd_payload_ras & (~sdram_bankmachine1_cmd_payload_cas)) & (~sdram_bankmachine1_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine1_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine1_cmd_payload_is_write == sdram_choose_req_want_writes)))); sdram_choose_req_valids[2] <= (sdram_bankmachine2_cmd_valid & (((sdram_bankmachine2_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine2_cmd_payload_ras & (~sdram_bankmachine2_cmd_payload_cas)) & (~sdram_bankmachine2_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine2_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine2_cmd_payload_is_write == sdram_choose_req_want_writes)))); sdram_choose_req_valids[3] <= (sdram_bankmachine3_cmd_valid & (((sdram_bankmachine3_cmd_payload_is_cmd & sdram_choose_req_want_cmds) & ((~((sdram_bankmachine3_cmd_payload_ras & (~sdram_bankmachine3_cmd_payload_cas)) & (~sdram_bankmachine3_cmd_payload_we))) | sdram_choose_req_want_activates)) | ((sdram_bankmachine3_cmd_payload_is_read == sdram_choose_req_want_reads) & (sdram_bankmachine3_cmd_payload_is_write == sdram_choose_req_want_writes)))); end assign sdram_choose_req_request = sdram_choose_req_valids; assign sdram_choose_req_cmd_valid = rhs_array_muxed6; assign sdram_choose_req_cmd_payload_a = rhs_array_muxed7; assign sdram_choose_req_cmd_payload_ba = rhs_array_muxed8; assign sdram_choose_req_cmd_payload_is_read = rhs_array_muxed9; assign sdram_choose_req_cmd_payload_is_write = rhs_array_muxed10; assign sdram_choose_req_cmd_payload_is_cmd = rhs_array_muxed11; always @(*) begin sdram_choose_req_cmd_payload_cas <= 1'd0; if (sdram_choose_req_cmd_valid) begin sdram_choose_req_cmd_payload_cas <= t_array_muxed3; end end always @(*) begin sdram_choose_req_cmd_payload_ras <= 1'd0; if (sdram_choose_req_cmd_valid) begin sdram_choose_req_cmd_payload_ras <= t_array_muxed4; end end always @(*) begin sdram_choose_req_cmd_payload_we <= 1'd0; if (sdram_choose_req_cmd_valid) begin sdram_choose_req_cmd_payload_we <= t_array_muxed5; end end always @(*) begin sdram_bankmachine0_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd0))) begin sdram_bankmachine0_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd0))) begin sdram_bankmachine0_cmd_ready <= 1'd1; end end always @(*) begin sdram_bankmachine1_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 1'd1))) begin sdram_bankmachine1_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 1'd1))) begin sdram_bankmachine1_cmd_ready <= 1'd1; end end always @(*) begin sdram_bankmachine2_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd2))) begin sdram_bankmachine2_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd2))) begin sdram_bankmachine2_cmd_ready <= 1'd1; end end always @(*) begin sdram_bankmachine3_cmd_ready <= 1'd0; if (((sdram_choose_cmd_cmd_valid & sdram_choose_cmd_cmd_ready) & (sdram_choose_cmd_grant == 2'd3))) begin sdram_bankmachine3_cmd_ready <= 1'd1; end if (((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & (sdram_choose_req_grant == 2'd3))) begin sdram_bankmachine3_cmd_ready <= 1'd1; end end assign sdram_choose_req_ce = (sdram_choose_req_cmd_ready | (~sdram_choose_req_cmd_valid)); assign sdram_dfi_p0_reset_n = 1'd1; assign sdram_dfi_p0_cke = {1{sdram_steerer0}}; assign sdram_dfi_p0_odt = {1{sdram_steerer1}}; always @(*) begin subfragments_multiplexer_next_state <= 3'd0; sdram_en1 <= 1'd0; sdram_choose_req_want_reads <= 1'd0; sdram_choose_req_want_writes <= 1'd0; sdram_cmd_ready <= 1'd0; sdram_choose_req_want_activates <= 1'd0; sdram_steerer_sel <= 2'd0; sdram_choose_req_cmd_ready <= 1'd0; sdram_en0 <= 1'd0; sdram_choose_req_want_activates <= sdram_ras_allowed; subfragments_multiplexer_next_state <= subfragments_multiplexer_state; case (subfragments_multiplexer_state) 1'd1: begin sdram_en1 <= 1'd1; sdram_choose_req_want_writes <= 1'd1; if (1'd1) begin sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed)); end else begin sdram_choose_req_want_activates <= sdram_ras_allowed; sdram_choose_req_cmd_ready <= ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed); sdram_choose_req_cmd_ready <= sdram_cas_allowed; end sdram_steerer_sel <= 2'd2; if (sdram_read_available) begin if (((~sdram_write_available) | sdram_max_time1)) begin subfragments_multiplexer_next_state <= 2'd3; end end if (sdram_go_to_refresh) begin subfragments_multiplexer_next_state <= 2'd2; end end 2'd2: begin sdram_steerer_sel <= 2'd3; sdram_cmd_ready <= 1'd1; if (sdram_cmd_last) begin subfragments_multiplexer_next_state <= 1'd0; end end 2'd3: begin if (sdram_twtrcon_ready) begin subfragments_multiplexer_next_state <= 1'd0; end end 3'd4: begin subfragments_multiplexer_next_state <= 3'd5; end 3'd5: begin subfragments_multiplexer_next_state <= 1'd1; end default: begin sdram_en0 <= 1'd1; sdram_choose_req_want_reads <= 1'd1; if (1'd1) begin sdram_choose_req_cmd_ready <= (sdram_cas_allowed & ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed)); end else begin sdram_choose_req_want_activates <= sdram_ras_allowed; sdram_choose_req_cmd_ready <= ((~((sdram_choose_req_cmd_payload_ras & (~sdram_choose_req_cmd_payload_cas)) & (~sdram_choose_req_cmd_payload_we))) | sdram_ras_allowed); sdram_choose_req_cmd_ready <= sdram_cas_allowed; end sdram_steerer_sel <= 2'd2; if (sdram_write_available) begin if (((~sdram_read_available) | sdram_max_time0)) begin subfragments_multiplexer_next_state <= 3'd4; end end if (sdram_go_to_refresh) begin subfragments_multiplexer_next_state <= 2'd2; end end endcase end assign subfragments_roundrobin0_request = {(((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin0_ce = ((~sdram_interface_bank0_valid) & (~sdram_interface_bank0_lock)); assign sdram_interface_bank0_addr = rhs_array_muxed12; assign sdram_interface_bank0_we = rhs_array_muxed13; assign sdram_interface_bank0_valid = rhs_array_muxed14; assign subfragments_roundrobin1_request = {(((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin1_ce = ((~sdram_interface_bank1_valid) & (~sdram_interface_bank1_lock)); assign sdram_interface_bank1_addr = rhs_array_muxed15; assign sdram_interface_bank1_we = rhs_array_muxed16; assign sdram_interface_bank1_valid = rhs_array_muxed17; assign subfragments_roundrobin2_request = {(((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin2_ce = ((~sdram_interface_bank2_valid) & (~sdram_interface_bank2_lock)); assign sdram_interface_bank2_addr = rhs_array_muxed18; assign sdram_interface_bank2_we = rhs_array_muxed19; assign sdram_interface_bank2_valid = rhs_array_muxed20; assign subfragments_roundrobin3_request = {(((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))))) & port_cmd_valid)}; assign subfragments_roundrobin3_ce = ((~sdram_interface_bank3_valid) & (~sdram_interface_bank3_lock)); assign sdram_interface_bank3_addr = rhs_array_muxed21; assign sdram_interface_bank3_we = rhs_array_muxed22; assign sdram_interface_bank3_valid = rhs_array_muxed23; assign port_cmd_ready = ((((1'd0 | (((subfragments_roundrobin0_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank0_ready)) | (((subfragments_roundrobin1_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank1_ready)) | (((subfragments_roundrobin2_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0)))))) & sdram_interface_bank2_ready)) | (((subfragments_roundrobin3_grant == 1'd0) & ((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0)))))) & sdram_interface_bank3_ready)); assign port_wdata_ready = subfragments_new_master_wdata_ready; assign port_rdata_valid = subfragments_new_master_rdata_valid3; always @(*) begin sdram_interface_wdata <= 16'd0; sdram_interface_wdata_we <= 2'd0; case ({subfragments_new_master_wdata_ready}) 1'd1: begin sdram_interface_wdata <= port_wdata_payload_data; sdram_interface_wdata_we <= port_wdata_payload_we; end default: begin sdram_interface_wdata <= 1'd0; sdram_interface_wdata_we <= 1'd0; end endcase end assign port_rdata_payload_data = sdram_interface_rdata; assign subfragments_roundrobin0_grant = 1'd0; assign subfragments_roundrobin1_grant = 1'd0; assign subfragments_roundrobin2_grant = 1'd0; assign subfragments_roundrobin3_grant = 1'd0; assign converter_reset = (~wb_sdram_cyc); always @(*) begin litedram_wb_dat_w <= 16'd0; case (converter_counter) 1'd0: begin litedram_wb_dat_w <= wb_sdram_dat_w[31:0]; end 1'd1: begin litedram_wb_dat_w <= wb_sdram_dat_w[31:16]; end endcase end assign wb_sdram_dat_r = {litedram_wb_dat_r, converter_dat_r[31:16]}; always @(*) begin litedram_wb_sel <= 2'd0; litedram_wb_cyc <= 1'd0; litedram_wb_stb <= 1'd0; subfragments_next_state <= 1'd0; converter_counter_subfragments_next_value <= 1'd0; litedram_wb_we <= 1'd0; converter_counter_subfragments_next_value_ce <= 1'd0; converter_skip <= 1'd0; wb_sdram_ack <= 1'd0; litedram_wb_adr <= 30'd0; subfragments_next_state <= subfragments_state; case (subfragments_state) 1'd1: begin litedram_wb_adr <= {wb_sdram_adr, converter_counter}; case (converter_counter) 1'd0: begin litedram_wb_sel <= wb_sdram_sel[3:0]; end 1'd1: begin litedram_wb_sel <= wb_sdram_sel[3:2]; end endcase if ((wb_sdram_stb & wb_sdram_cyc)) begin converter_skip <= (litedram_wb_sel == 1'd0); litedram_wb_we <= wb_sdram_we; litedram_wb_cyc <= (~converter_skip); litedram_wb_stb <= (~converter_skip); if ((litedram_wb_ack | converter_skip)) begin converter_counter_subfragments_next_value <= (converter_counter + 1'd1); converter_counter_subfragments_next_value_ce <= 1'd1; if ((converter_counter == 1'd1)) begin wb_sdram_ack <= 1'd1; subfragments_next_state <= 1'd0; end end end end default: begin converter_counter_subfragments_next_value <= 1'd0; converter_counter_subfragments_next_value_ce <= 1'd1; if ((wb_sdram_stb & wb_sdram_cyc)) begin subfragments_next_state <= 1'd1; end end endcase end assign port_cmd_payload_addr = (litedram_wb_adr - 31'd1207959552); assign port_cmd_payload_we = litedram_wb_we; assign port_wdata_payload_data = litedram_wb_dat_w; assign port_wdata_payload_we = litedram_wb_sel; assign litedram_wb_dat_r = port_rdata_payload_data; assign port_flush = (~litedram_wb_cyc); assign port_cmd_last = (~litedram_wb_we); assign port_cmd_valid = ((litedram_wb_cyc & litedram_wb_stb) & (~cmd_consumed)); assign port_wdata_valid = (((port_cmd_valid | cmd_consumed) & port_cmd_payload_we) & (~wdata_consumed)); assign port_rdata_ready = ((port_cmd_valid | cmd_consumed) & (~port_cmd_payload_we)); assign litedram_wb_ack = (ack_cmd & ((litedram_wb_we & ack_wdata) | ((~litedram_wb_we) & ack_rdata))); assign ack_cmd = ((port_cmd_valid & port_cmd_ready) | cmd_consumed); assign ack_wdata = ((port_wdata_valid & port_wdata_ready) | wdata_consumed); assign ack_rdata = (port_rdata_valid & port_rdata_ready); assign uart_sink_valid = uart_phy_source_valid; assign uart_phy_source_ready = uart_sink_ready; assign uart_sink_first = uart_phy_source_first; assign uart_sink_last = uart_phy_source_last; assign uart_sink_payload_data = uart_phy_source_payload_data; assign uart_phy_sink_valid = uart_source_valid; assign uart_source_ready = uart_phy_sink_ready; assign uart_phy_sink_first = uart_source_first; assign uart_phy_sink_last = uart_source_last; assign uart_phy_sink_payload_data = uart_source_payload_data; assign tx_fifo_sink_valid = rxtx_re; assign tx_fifo_sink_payload_data = rxtx_r; assign txfull_status = (~tx_fifo_sink_ready); assign txempty_status = (~tx_fifo_source_valid); assign uart_source_valid = tx_fifo_source_valid; assign tx_fifo_source_ready = uart_source_ready; assign uart_source_first = tx_fifo_source_first; assign uart_source_last = tx_fifo_source_last; assign uart_source_payload_data = tx_fifo_source_payload_data; assign tx_trigger = (~tx_fifo_sink_ready); assign rx_fifo_sink_valid = uart_sink_valid; assign uart_sink_ready = rx_fifo_sink_ready; assign rx_fifo_sink_first = uart_sink_first; assign rx_fifo_sink_last = uart_sink_last; assign rx_fifo_sink_payload_data = uart_sink_payload_data; assign rxempty_status = (~rx_fifo_source_valid); assign rxfull_status = (~rx_fifo_sink_ready); assign rxtx_w = rx_fifo_source_payload_data; assign rx_fifo_source_ready = (rx_clear | (1'd0 & rxtx_we)); assign rx_trigger = (~rx_fifo_source_valid); always @(*) begin tx_clear <= 1'd0; if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin tx_clear <= 1'd1; end end always @(*) begin eventmanager_status_w <= 2'd0; eventmanager_status_w[0] <= tx_status; eventmanager_status_w[1] <= rx_status; end always @(*) begin rx_clear <= 1'd0; if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin rx_clear <= 1'd1; end end always @(*) begin eventmanager_pending_w <= 2'd0; eventmanager_pending_w[0] <= tx_pending; eventmanager_pending_w[1] <= rx_pending; end assign irq = ((eventmanager_pending_w[0] & eventmanager_storage[0]) | (eventmanager_pending_w[1] & eventmanager_storage[1])); assign tx_status = tx_trigger; assign rx_status = rx_trigger; assign tx_fifo_syncfifo_din = {tx_fifo_fifo_in_last, tx_fifo_fifo_in_first, tx_fifo_fifo_in_payload_data}; assign {tx_fifo_fifo_out_last, tx_fifo_fifo_out_first, tx_fifo_fifo_out_payload_data} = tx_fifo_syncfifo_dout; assign tx_fifo_sink_ready = tx_fifo_syncfifo_writable; assign tx_fifo_syncfifo_we = tx_fifo_sink_valid; assign tx_fifo_fifo_in_first = tx_fifo_sink_first; assign tx_fifo_fifo_in_last = tx_fifo_sink_last; assign tx_fifo_fifo_in_payload_data = tx_fifo_sink_payload_data; assign tx_fifo_source_valid = tx_fifo_readable; assign tx_fifo_source_first = tx_fifo_fifo_out_first; assign tx_fifo_source_last = tx_fifo_fifo_out_last; assign tx_fifo_source_payload_data = tx_fifo_fifo_out_payload_data; assign tx_fifo_re = tx_fifo_source_ready; assign tx_fifo_syncfifo_re = (tx_fifo_syncfifo_readable & ((~tx_fifo_readable) | tx_fifo_re)); assign tx_fifo_level1 = (tx_fifo_level0 + tx_fifo_readable); always @(*) begin tx_fifo_wrport_adr <= 4'd0; if (tx_fifo_replace) begin tx_fifo_wrport_adr <= (tx_fifo_produce - 1'd1); end else begin tx_fifo_wrport_adr <= tx_fifo_produce; end end assign tx_fifo_wrport_dat_w = tx_fifo_syncfifo_din; assign tx_fifo_wrport_we = (tx_fifo_syncfifo_we & (tx_fifo_syncfifo_writable | tx_fifo_replace)); assign tx_fifo_do_read = (tx_fifo_syncfifo_readable & tx_fifo_syncfifo_re); assign tx_fifo_rdport_adr = tx_fifo_consume; assign tx_fifo_syncfifo_dout = tx_fifo_rdport_dat_r; assign tx_fifo_rdport_re = tx_fifo_do_read; assign tx_fifo_syncfifo_writable = (tx_fifo_level0 != 5'd16); assign tx_fifo_syncfifo_readable = (tx_fifo_level0 != 1'd0); assign rx_fifo_syncfifo_din = {rx_fifo_fifo_in_last, rx_fifo_fifo_in_first, rx_fifo_fifo_in_payload_data}; assign {rx_fifo_fifo_out_last, rx_fifo_fifo_out_first, rx_fifo_fifo_out_payload_data} = rx_fifo_syncfifo_dout; assign rx_fifo_sink_ready = rx_fifo_syncfifo_writable; assign rx_fifo_syncfifo_we = rx_fifo_sink_valid; assign rx_fifo_fifo_in_first = rx_fifo_sink_first; assign rx_fifo_fifo_in_last = rx_fifo_sink_last; assign rx_fifo_fifo_in_payload_data = rx_fifo_sink_payload_data; assign rx_fifo_source_valid = rx_fifo_readable; assign rx_fifo_source_first = rx_fifo_fifo_out_first; assign rx_fifo_source_last = rx_fifo_fifo_out_last; assign rx_fifo_source_payload_data = rx_fifo_fifo_out_payload_data; assign rx_fifo_re = rx_fifo_source_ready; assign rx_fifo_syncfifo_re = (rx_fifo_syncfifo_readable & ((~rx_fifo_readable) | rx_fifo_re)); assign rx_fifo_level1 = (rx_fifo_level0 + rx_fifo_readable); always @(*) begin rx_fifo_wrport_adr <= 4'd0; if (rx_fifo_replace) begin rx_fifo_wrport_adr <= (rx_fifo_produce - 1'd1); end else begin rx_fifo_wrport_adr <= rx_fifo_produce; end end assign rx_fifo_wrport_dat_w = rx_fifo_syncfifo_din; assign rx_fifo_wrport_we = (rx_fifo_syncfifo_we & (rx_fifo_syncfifo_writable | rx_fifo_replace)); assign rx_fifo_do_read = (rx_fifo_syncfifo_readable & rx_fifo_syncfifo_re); assign rx_fifo_rdport_adr = rx_fifo_consume; assign rx_fifo_syncfifo_dout = rx_fifo_rdport_dat_r; assign rx_fifo_rdport_re = rx_fifo_do_read; assign rx_fifo_syncfifo_writable = (rx_fifo_level0 != 5'd16); assign rx_fifo_syncfifo_readable = (rx_fifo_level0 != 1'd0); always @(*) begin gpio0_pads_gpio0i <= 8'd0; gpio0_pads_gpio0i[0] <= libresocsim_libresoc_constraintmanager_gpio_i[0]; gpio0_pads_gpio0i[1] <= libresocsim_libresoc_constraintmanager_gpio_i[1]; gpio0_pads_gpio0i[2] <= libresocsim_libresoc_constraintmanager_gpio_i[2]; gpio0_pads_gpio0i[3] <= libresocsim_libresoc_constraintmanager_gpio_i[3]; gpio0_pads_gpio0i[4] <= libresocsim_libresoc_constraintmanager_gpio_i[4]; gpio0_pads_gpio0i[5] <= libresocsim_libresoc_constraintmanager_gpio_i[5]; gpio0_pads_gpio0i[6] <= libresocsim_libresoc_constraintmanager_gpio_i[6]; gpio0_pads_gpio0i[7] <= libresocsim_libresoc_constraintmanager_gpio_i[7]; end always @(*) begin gpio1_pads_gpio1i <= 8'd0; gpio1_pads_gpio1i[0] <= libresocsim_libresoc_constraintmanager_gpio_i[8]; gpio1_pads_gpio1i[1] <= libresocsim_libresoc_constraintmanager_gpio_i[9]; gpio1_pads_gpio1i[2] <= libresocsim_libresoc_constraintmanager_gpio_i[10]; gpio1_pads_gpio1i[3] <= libresocsim_libresoc_constraintmanager_gpio_i[11]; gpio1_pads_gpio1i[4] <= libresocsim_libresoc_constraintmanager_gpio_i[12]; gpio1_pads_gpio1i[5] <= libresocsim_libresoc_constraintmanager_gpio_i[13]; gpio1_pads_gpio1i[6] <= libresocsim_libresoc_constraintmanager_gpio_i[14]; gpio1_pads_gpio1i[7] <= libresocsim_libresoc_constraintmanager_gpio_i[15]; end always @(*) begin libresocsim_libresoc_constraintmanager_gpio_o <= 16'd0; libresocsim_libresoc_constraintmanager_gpio_o[0] <= gpio0_pads_gpio0o[0]; libresocsim_libresoc_constraintmanager_gpio_o[1] <= gpio0_pads_gpio0o[1]; libresocsim_libresoc_constraintmanager_gpio_o[2] <= gpio0_pads_gpio0o[2]; libresocsim_libresoc_constraintmanager_gpio_o[3] <= gpio0_pads_gpio0o[3]; libresocsim_libresoc_constraintmanager_gpio_o[4] <= gpio0_pads_gpio0o[4]; libresocsim_libresoc_constraintmanager_gpio_o[5] <= gpio0_pads_gpio0o[5]; libresocsim_libresoc_constraintmanager_gpio_o[6] <= gpio0_pads_gpio0o[6]; libresocsim_libresoc_constraintmanager_gpio_o[7] <= gpio0_pads_gpio0o[7]; libresocsim_libresoc_constraintmanager_gpio_o[8] <= gpio1_pads_gpio1o[0]; libresocsim_libresoc_constraintmanager_gpio_o[9] <= gpio1_pads_gpio1o[1]; libresocsim_libresoc_constraintmanager_gpio_o[10] <= gpio1_pads_gpio1o[2]; libresocsim_libresoc_constraintmanager_gpio_o[11] <= gpio1_pads_gpio1o[3]; libresocsim_libresoc_constraintmanager_gpio_o[12] <= gpio1_pads_gpio1o[4]; libresocsim_libresoc_constraintmanager_gpio_o[13] <= gpio1_pads_gpio1o[5]; libresocsim_libresoc_constraintmanager_gpio_o[14] <= gpio1_pads_gpio1o[6]; libresocsim_libresoc_constraintmanager_gpio_o[15] <= gpio1_pads_gpio1o[7]; end always @(*) begin libresocsim_libresoc_constraintmanager_gpio_oe <= 16'd0; libresocsim_libresoc_constraintmanager_gpio_oe[0] <= gpio0_pads_gpio0oe[0]; libresocsim_libresoc_constraintmanager_gpio_oe[1] <= gpio0_pads_gpio0oe[1]; libresocsim_libresoc_constraintmanager_gpio_oe[2] <= gpio0_pads_gpio0oe[2]; libresocsim_libresoc_constraintmanager_gpio_oe[3] <= gpio0_pads_gpio0oe[3]; libresocsim_libresoc_constraintmanager_gpio_oe[4] <= gpio0_pads_gpio0oe[4]; libresocsim_libresoc_constraintmanager_gpio_oe[5] <= gpio0_pads_gpio0oe[5]; libresocsim_libresoc_constraintmanager_gpio_oe[6] <= gpio0_pads_gpio0oe[6]; libresocsim_libresoc_constraintmanager_gpio_oe[7] <= gpio0_pads_gpio0oe[7]; libresocsim_libresoc_constraintmanager_gpio_oe[8] <= gpio1_pads_gpio1oe[0]; libresocsim_libresoc_constraintmanager_gpio_oe[9] <= gpio1_pads_gpio1oe[1]; libresocsim_libresoc_constraintmanager_gpio_oe[10] <= gpio1_pads_gpio1oe[2]; libresocsim_libresoc_constraintmanager_gpio_oe[11] <= gpio1_pads_gpio1oe[3]; libresocsim_libresoc_constraintmanager_gpio_oe[12] <= gpio1_pads_gpio1oe[4]; libresocsim_libresoc_constraintmanager_gpio_oe[13] <= gpio1_pads_gpio1oe[5]; libresocsim_libresoc_constraintmanager_gpio_oe[14] <= gpio1_pads_gpio1oe[6]; libresocsim_libresoc_constraintmanager_gpio_oe[15] <= gpio1_pads_gpio1oe[7]; end assign libresocsim_libresoc_constraintmanager_i2c_scl = i2c_scl_1; assign libresocsim_libresoc_constraintmanager_i2c_sda_oe = i2c_oe; assign libresocsim_libresoc_constraintmanager_i2c_sda_o = i2c_sda0; assign i2c_sda1 = libresocsim_libresoc_constraintmanager_i2c_sda_i; always @(*) begin libresocsim_next_state <= 2'd0; libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= 8'd0; libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd0; libresocsim_libresocsim_adr_libresocsim_next_value1 <= 13'd0; libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd0; libresocsim_libresocsim_wishbone_dat_r <= 32'd0; libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0; libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd0; libresocsim_libresocsim_wishbone_ack <= 1'd0; libresocsim_next_state <= libresocsim_state; case (libresocsim_state) 1'd1: begin libresocsim_libresocsim_adr_libresocsim_next_value1 <= 1'd0; libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1; libresocsim_libresocsim_we_libresocsim_next_value2 <= 1'd0; libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1; libresocsim_next_state <= 2'd2; end 2'd2: begin libresocsim_libresocsim_wishbone_ack <= 1'd1; libresocsim_libresocsim_wishbone_dat_r <= libresocsim_libresocsim_dat_r; libresocsim_next_state <= 1'd0; end default: begin libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= libresocsim_libresocsim_wishbone_dat_w; libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= 1'd1; if ((libresocsim_libresocsim_wishbone_cyc & libresocsim_libresocsim_wishbone_stb)) begin libresocsim_libresocsim_adr_libresocsim_next_value1 <= libresocsim_libresocsim_wishbone_adr; libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= 1'd1; libresocsim_libresocsim_we_libresocsim_next_value2 <= (libresocsim_libresocsim_wishbone_we & (libresocsim_libresocsim_wishbone_sel != 1'd0)); libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= 1'd1; libresocsim_next_state <= 1'd1; end end endcase end assign libresocsim_shared_adr = rhs_array_muxed24; assign libresocsim_shared_dat_w = rhs_array_muxed25; assign libresocsim_shared_sel = rhs_array_muxed26; assign libresocsim_shared_cyc = rhs_array_muxed27; assign libresocsim_shared_stb = rhs_array_muxed28; assign libresocsim_shared_we = rhs_array_muxed29; assign libresocsim_shared_cti = rhs_array_muxed30; assign libresocsim_shared_bte = rhs_array_muxed31; assign libresocsim_interface0_converted_interface_dat_r = libresocsim_shared_dat_r; assign libresocsim_interface1_converted_interface_dat_r = libresocsim_shared_dat_r; assign libresocsim_libresoc_jtag_wb_dat_r = libresocsim_shared_dat_r; assign libresocsim_interface0_converted_interface_ack = (libresocsim_shared_ack & (libresocsim_grant == 1'd0)); assign libresocsim_interface1_converted_interface_ack = (libresocsim_shared_ack & (libresocsim_grant == 1'd1)); assign libresocsim_libresoc_jtag_wb_ack = (libresocsim_shared_ack & (libresocsim_grant == 2'd2)); assign libresocsim_interface0_converted_interface_err = (libresocsim_shared_err & (libresocsim_grant == 1'd0)); assign libresocsim_interface1_converted_interface_err = (libresocsim_shared_err & (libresocsim_grant == 1'd1)); assign libresocsim_libresoc_jtag_wb_err = (libresocsim_shared_err & (libresocsim_grant == 2'd2)); assign libresocsim_request = {libresocsim_libresoc_jtag_wb_cyc, libresocsim_interface1_converted_interface_cyc, libresocsim_interface0_converted_interface_cyc}; always @(*) begin libresocsim_slave_sel <= 6'd0; libresocsim_slave_sel[0] <= (libresocsim_shared_adr[29:7] == 1'd0); libresocsim_slave_sel[1] <= (libresocsim_shared_adr[29:5] == 4'd14); libresocsim_slave_sel[2] <= (libresocsim_shared_adr[29:3] == 27'd100665344); libresocsim_slave_sel[3] <= (libresocsim_shared_adr[29:10] == 20'd786449); libresocsim_slave_sel[4] <= (libresocsim_shared_adr[29:23] == 7'd72); libresocsim_slave_sel[5] <= (libresocsim_shared_adr[29:13] == 17'd98304); end assign libresocsim_ram_bus_adr = libresocsim_shared_adr; assign libresocsim_ram_bus_dat_w = libresocsim_shared_dat_w; assign libresocsim_ram_bus_sel = libresocsim_shared_sel; assign libresocsim_ram_bus_stb = libresocsim_shared_stb; assign libresocsim_ram_bus_we = libresocsim_shared_we; assign libresocsim_ram_bus_cti = libresocsim_shared_cti; assign libresocsim_ram_bus_bte = libresocsim_shared_bte; assign ram_bus_ram_bus_adr = libresocsim_shared_adr; assign ram_bus_ram_bus_dat_w = libresocsim_shared_dat_w; assign ram_bus_ram_bus_sel = libresocsim_shared_sel; assign ram_bus_ram_bus_stb = libresocsim_shared_stb; assign ram_bus_ram_bus_we = libresocsim_shared_we; assign ram_bus_ram_bus_cti = libresocsim_shared_cti; assign ram_bus_ram_bus_bte = libresocsim_shared_bte; assign libresocsim_libresoc_xics_icp_adr = libresocsim_shared_adr; assign libresocsim_libresoc_xics_icp_dat_w = libresocsim_shared_dat_w; assign libresocsim_libresoc_xics_icp_sel = libresocsim_shared_sel; assign libresocsim_libresoc_xics_icp_stb = libresocsim_shared_stb; assign libresocsim_libresoc_xics_icp_we = libresocsim_shared_we; assign libresocsim_libresoc_xics_icp_cti = libresocsim_shared_cti; assign libresocsim_libresoc_xics_icp_bte = libresocsim_shared_bte; assign libresocsim_libresoc_xics_ics_adr = libresocsim_shared_adr; assign libresocsim_libresoc_xics_ics_dat_w = libresocsim_shared_dat_w; assign libresocsim_libresoc_xics_ics_sel = libresocsim_shared_sel; assign libresocsim_libresoc_xics_ics_stb = libresocsim_shared_stb; assign libresocsim_libresoc_xics_ics_we = libresocsim_shared_we; assign libresocsim_libresoc_xics_ics_cti = libresocsim_shared_cti; assign libresocsim_libresoc_xics_ics_bte = libresocsim_shared_bte; assign wb_sdram_adr = libresocsim_shared_adr; assign wb_sdram_dat_w = libresocsim_shared_dat_w; assign wb_sdram_sel = libresocsim_shared_sel; assign wb_sdram_stb = libresocsim_shared_stb; assign wb_sdram_we = libresocsim_shared_we; assign wb_sdram_cti = libresocsim_shared_cti; assign wb_sdram_bte = libresocsim_shared_bte; assign libresocsim_libresocsim_wishbone_adr = libresocsim_shared_adr; assign libresocsim_libresocsim_wishbone_dat_w = libresocsim_shared_dat_w; assign libresocsim_libresocsim_wishbone_sel = libresocsim_shared_sel; assign libresocsim_libresocsim_wishbone_stb = libresocsim_shared_stb; assign libresocsim_libresocsim_wishbone_we = libresocsim_shared_we; assign libresocsim_libresocsim_wishbone_cti = libresocsim_shared_cti; assign libresocsim_libresocsim_wishbone_bte = libresocsim_shared_bte; assign libresocsim_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[0]); assign ram_bus_ram_bus_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[1]); assign libresocsim_libresoc_xics_icp_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[2]); assign libresocsim_libresoc_xics_ics_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[3]); assign wb_sdram_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[4]); assign libresocsim_libresocsim_wishbone_cyc = (libresocsim_shared_cyc & libresocsim_slave_sel[5]); assign libresocsim_shared_err = (((((libresocsim_ram_bus_err | ram_bus_ram_bus_err) | libresocsim_libresoc_xics_icp_err) | libresocsim_libresoc_xics_ics_err) | wb_sdram_err) | libresocsim_libresocsim_wishbone_err); assign libresocsim_wait = ((libresocsim_shared_stb & libresocsim_shared_cyc) & (~libresocsim_shared_ack)); always @(*) begin libresocsim_shared_ack <= 1'd0; libresocsim_error <= 1'd0; libresocsim_shared_dat_r <= 32'd0; libresocsim_shared_ack <= (((((libresocsim_ram_bus_ack | ram_bus_ram_bus_ack) | libresocsim_libresoc_xics_icp_ack) | libresocsim_libresoc_xics_ics_ack) | wb_sdram_ack) | libresocsim_libresocsim_wishbone_ack); libresocsim_shared_dat_r <= (((((({32{libresocsim_slave_sel_r[0]}} & libresocsim_ram_bus_dat_r) | ({32{libresocsim_slave_sel_r[1]}} & ram_bus_ram_bus_dat_r)) | ({32{libresocsim_slave_sel_r[2]}} & libresocsim_libresoc_xics_icp_dat_r)) | ({32{libresocsim_slave_sel_r[3]}} & libresocsim_libresoc_xics_ics_dat_r)) | ({32{libresocsim_slave_sel_r[4]}} & wb_sdram_dat_r)) | ({32{libresocsim_slave_sel_r[5]}} & libresocsim_libresocsim_wishbone_dat_r)); if (libresocsim_done) begin libresocsim_shared_dat_r <= 32'd4294967295; libresocsim_shared_ack <= 1'd1; libresocsim_error <= 1'd1; end end assign libresocsim_done = (libresocsim_count == 1'd0); assign libresocsim_csrbank0_sel = (libresocsim_interface0_bank_bus_adr[12:9] == 1'd0); assign libresocsim_csrbank0_reset0_r = libresocsim_interface0_bank_bus_dat_w[0]; assign libresocsim_csrbank0_reset0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd0)); assign libresocsim_csrbank0_reset0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd0)); assign libresocsim_csrbank0_scratch3_r = libresocsim_interface0_bank_bus_dat_w[7:0]; assign libresocsim_csrbank0_scratch3_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd1)); assign libresocsim_csrbank0_scratch3_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 1'd1)); assign libresocsim_csrbank0_scratch2_r = libresocsim_interface0_bank_bus_dat_w[7:0]; assign libresocsim_csrbank0_scratch2_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd2)); assign libresocsim_csrbank0_scratch2_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd2)); assign libresocsim_csrbank0_scratch1_r = libresocsim_interface0_bank_bus_dat_w[7:0]; assign libresocsim_csrbank0_scratch1_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd3)); assign libresocsim_csrbank0_scratch1_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 2'd3)); assign libresocsim_csrbank0_scratch0_r = libresocsim_interface0_bank_bus_dat_w[7:0]; assign libresocsim_csrbank0_scratch0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd4)); assign libresocsim_csrbank0_scratch0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd4)); assign libresocsim_csrbank0_bus_errors3_r = libresocsim_interface0_bank_bus_dat_w[7:0]; assign libresocsim_csrbank0_bus_errors3_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd5)); assign libresocsim_csrbank0_bus_errors3_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd5)); assign libresocsim_csrbank0_bus_errors2_r = libresocsim_interface0_bank_bus_dat_w[7:0]; assign libresocsim_csrbank0_bus_errors2_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd6)); assign libresocsim_csrbank0_bus_errors2_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd6)); assign libresocsim_csrbank0_bus_errors1_r = libresocsim_interface0_bank_bus_dat_w[7:0]; assign libresocsim_csrbank0_bus_errors1_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd7)); assign libresocsim_csrbank0_bus_errors1_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 3'd7)); assign libresocsim_csrbank0_bus_errors0_r = libresocsim_interface0_bank_bus_dat_w[7:0]; assign libresocsim_csrbank0_bus_errors0_re = ((libresocsim_csrbank0_sel & libresocsim_interface0_bank_bus_we) & (libresocsim_interface0_bank_bus_adr[3:0] == 4'd8)); assign libresocsim_csrbank0_bus_errors0_we = ((libresocsim_csrbank0_sel & (~libresocsim_interface0_bank_bus_we)) & (libresocsim_interface0_bank_bus_adr[3:0] == 4'd8)); assign libresocsim_csrbank0_reset0_w = libresocsim_reset_storage; assign libresocsim_csrbank0_scratch3_w = libresocsim_scratch_storage[31:24]; assign libresocsim_csrbank0_scratch2_w = libresocsim_scratch_storage[23:16]; assign libresocsim_csrbank0_scratch1_w = libresocsim_scratch_storage[15:8]; assign libresocsim_csrbank0_scratch0_w = libresocsim_scratch_storage[7:0]; assign libresocsim_csrbank0_bus_errors3_w = libresocsim_bus_errors_status[31:24]; assign libresocsim_csrbank0_bus_errors2_w = libresocsim_bus_errors_status[23:16]; assign libresocsim_csrbank0_bus_errors1_w = libresocsim_bus_errors_status[15:8]; assign libresocsim_csrbank0_bus_errors0_w = libresocsim_bus_errors_status[7:0]; assign libresocsim_bus_errors_we = libresocsim_csrbank0_bus_errors0_we; assign libresocsim_csrbank1_sel = (libresocsim_interface1_bank_bus_adr[12:9] == 3'd6); assign libresocsim_csrbank1_oe0_r = libresocsim_interface1_bank_bus_dat_w[7:0]; assign libresocsim_csrbank1_oe0_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd0)); assign libresocsim_csrbank1_oe0_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd0)); assign libresocsim_csrbank1_in_r = libresocsim_interface1_bank_bus_dat_w[7:0]; assign libresocsim_csrbank1_in_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd1)); assign libresocsim_csrbank1_in_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 1'd1)); assign libresocsim_csrbank1_out0_r = libresocsim_interface1_bank_bus_dat_w[7:0]; assign libresocsim_csrbank1_out0_re = ((libresocsim_csrbank1_sel & libresocsim_interface1_bank_bus_we) & (libresocsim_interface1_bank_bus_adr[1:0] == 2'd2)); assign libresocsim_csrbank1_out0_we = ((libresocsim_csrbank1_sel & (~libresocsim_interface1_bank_bus_we)) & (libresocsim_interface1_bank_bus_adr[1:0] == 2'd2)); assign libresocsim_csrbank1_oe0_w = gpio0_oe_storage[7:0]; assign libresocsim_csrbank1_in_w = gpio0_status[7:0]; assign gpio0_we = libresocsim_csrbank1_in_we; assign libresocsim_csrbank1_out0_w = gpio0_out_storage[7:0]; assign libresocsim_csrbank2_sel = (libresocsim_interface2_bank_bus_adr[12:9] == 3'd7); assign libresocsim_csrbank2_oe0_r = libresocsim_interface2_bank_bus_dat_w[7:0]; assign libresocsim_csrbank2_oe0_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd0)); assign libresocsim_csrbank2_oe0_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd0)); assign libresocsim_csrbank2_in_r = libresocsim_interface2_bank_bus_dat_w[7:0]; assign libresocsim_csrbank2_in_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd1)); assign libresocsim_csrbank2_in_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 1'd1)); assign libresocsim_csrbank2_out0_r = libresocsim_interface2_bank_bus_dat_w[7:0]; assign libresocsim_csrbank2_out0_re = ((libresocsim_csrbank2_sel & libresocsim_interface2_bank_bus_we) & (libresocsim_interface2_bank_bus_adr[1:0] == 2'd2)); assign libresocsim_csrbank2_out0_we = ((libresocsim_csrbank2_sel & (~libresocsim_interface2_bank_bus_we)) & (libresocsim_interface2_bank_bus_adr[1:0] == 2'd2)); assign libresocsim_csrbank2_oe0_w = gpio1_oe_storage[7:0]; assign libresocsim_csrbank2_in_w = gpio1_status[7:0]; assign gpio1_we = libresocsim_csrbank2_in_we; assign libresocsim_csrbank2_out0_w = gpio1_out_storage[7:0]; assign libresocsim_csrbank3_sel = (libresocsim_interface3_bank_bus_adr[12:9] == 4'd8); assign libresocsim_csrbank3_w0_r = libresocsim_interface3_bank_bus_dat_w[2:0]; assign libresocsim_csrbank3_w0_re = ((libresocsim_csrbank3_sel & libresocsim_interface3_bank_bus_we) & (libresocsim_interface3_bank_bus_adr[0] == 1'd0)); assign libresocsim_csrbank3_w0_we = ((libresocsim_csrbank3_sel & (~libresocsim_interface3_bank_bus_we)) & (libresocsim_interface3_bank_bus_adr[0] == 1'd0)); assign libresocsim_csrbank3_r_r = libresocsim_interface3_bank_bus_dat_w[0]; assign libresocsim_csrbank3_r_re = ((libresocsim_csrbank3_sel & libresocsim_interface3_bank_bus_we) & (libresocsim_interface3_bank_bus_adr[0] == 1'd1)); assign libresocsim_csrbank3_r_we = ((libresocsim_csrbank3_sel & (~libresocsim_interface3_bank_bus_we)) & (libresocsim_interface3_bank_bus_adr[0] == 1'd1)); assign i2c_scl_1 = i2c_storage[0]; assign i2c_oe = i2c_storage[1]; assign i2c_sda0 = i2c_storage[2]; assign libresocsim_csrbank3_w0_w = i2c_storage[2:0]; assign i2c_status = i2c_sda1; assign libresocsim_csrbank3_r_w = i2c_status; assign i2c_we = libresocsim_csrbank3_r_we; assign libresocsim_csrbank4_sel = (libresocsim_interface4_bank_bus_adr[12:9] == 2'd3); assign libresocsim_csrbank4_dfii_control0_r = libresocsim_interface4_bank_bus_dat_w[3:0]; assign libresocsim_csrbank4_dfii_control0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd0)); assign libresocsim_csrbank4_dfii_control0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd0)); assign libresocsim_csrbank4_dfii_pi0_command0_r = libresocsim_interface4_bank_bus_dat_w[5:0]; assign libresocsim_csrbank4_dfii_pi0_command0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd1)); assign libresocsim_csrbank4_dfii_pi0_command0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 1'd1)); assign sdram_command_issue_r = libresocsim_interface4_bank_bus_dat_w[0]; assign sdram_command_issue_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd2)); assign sdram_command_issue_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd2)); assign libresocsim_csrbank4_dfii_pi0_address1_r = libresocsim_interface4_bank_bus_dat_w[4:0]; assign libresocsim_csrbank4_dfii_pi0_address1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd3)); assign libresocsim_csrbank4_dfii_pi0_address1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 2'd3)); assign libresocsim_csrbank4_dfii_pi0_address0_r = libresocsim_interface4_bank_bus_dat_w[7:0]; assign libresocsim_csrbank4_dfii_pi0_address0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd4)); assign libresocsim_csrbank4_dfii_pi0_address0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd4)); assign libresocsim_csrbank4_dfii_pi0_baddress0_r = libresocsim_interface4_bank_bus_dat_w[1:0]; assign libresocsim_csrbank4_dfii_pi0_baddress0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd5)); assign libresocsim_csrbank4_dfii_pi0_baddress0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd5)); assign libresocsim_csrbank4_dfii_pi0_wrdata1_r = libresocsim_interface4_bank_bus_dat_w[7:0]; assign libresocsim_csrbank4_dfii_pi0_wrdata1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd6)); assign libresocsim_csrbank4_dfii_pi0_wrdata1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd6)); assign libresocsim_csrbank4_dfii_pi0_wrdata0_r = libresocsim_interface4_bank_bus_dat_w[7:0]; assign libresocsim_csrbank4_dfii_pi0_wrdata0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd7)); assign libresocsim_csrbank4_dfii_pi0_wrdata0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 3'd7)); assign libresocsim_csrbank4_dfii_pi0_rddata1_r = libresocsim_interface4_bank_bus_dat_w[7:0]; assign libresocsim_csrbank4_dfii_pi0_rddata1_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd8)); assign libresocsim_csrbank4_dfii_pi0_rddata1_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd8)); assign libresocsim_csrbank4_dfii_pi0_rddata0_r = libresocsim_interface4_bank_bus_dat_w[7:0]; assign libresocsim_csrbank4_dfii_pi0_rddata0_re = ((libresocsim_csrbank4_sel & libresocsim_interface4_bank_bus_we) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd9)); assign libresocsim_csrbank4_dfii_pi0_rddata0_we = ((libresocsim_csrbank4_sel & (~libresocsim_interface4_bank_bus_we)) & (libresocsim_interface4_bank_bus_adr[3:0] == 4'd9)); assign sdram_sel = sdram_storage[0]; assign sdram_cke_1 = sdram_storage[1]; assign sdram_odt = sdram_storage[2]; assign sdram_reset_n = sdram_storage[3]; assign libresocsim_csrbank4_dfii_control0_w = sdram_storage[3:0]; assign libresocsim_csrbank4_dfii_pi0_command0_w = sdram_command_storage[5:0]; assign libresocsim_csrbank4_dfii_pi0_address1_w = sdram_address_storage[12:8]; assign libresocsim_csrbank4_dfii_pi0_address0_w = sdram_address_storage[7:0]; assign libresocsim_csrbank4_dfii_pi0_baddress0_w = sdram_baddress_storage[1:0]; assign libresocsim_csrbank4_dfii_pi0_wrdata1_w = sdram_wrdata_storage[15:8]; assign libresocsim_csrbank4_dfii_pi0_wrdata0_w = sdram_wrdata_storage[7:0]; assign libresocsim_csrbank4_dfii_pi0_rddata1_w = sdram_status[15:8]; assign libresocsim_csrbank4_dfii_pi0_rddata0_w = sdram_status[7:0]; assign sdram_we = libresocsim_csrbank4_dfii_pi0_rddata0_we; assign libresocsim_csrbank5_sel = (libresocsim_interface5_bank_bus_adr[12:9] == 2'd2); assign libresocsim_csrbank5_load3_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_load3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd0)); assign libresocsim_csrbank5_load3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd0)); assign libresocsim_csrbank5_load2_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_load2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd1)); assign libresocsim_csrbank5_load2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 1'd1)); assign libresocsim_csrbank5_load1_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_load1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd2)); assign libresocsim_csrbank5_load1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd2)); assign libresocsim_csrbank5_load0_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_load0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd3)); assign libresocsim_csrbank5_load0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 2'd3)); assign libresocsim_csrbank5_reload3_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_reload3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd4)); assign libresocsim_csrbank5_reload3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd4)); assign libresocsim_csrbank5_reload2_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_reload2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd5)); assign libresocsim_csrbank5_reload2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd5)); assign libresocsim_csrbank5_reload1_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_reload1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd6)); assign libresocsim_csrbank5_reload1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd6)); assign libresocsim_csrbank5_reload0_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_reload0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd7)); assign libresocsim_csrbank5_reload0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 3'd7)); assign libresocsim_csrbank5_en0_r = libresocsim_interface5_bank_bus_dat_w[0]; assign libresocsim_csrbank5_en0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd8)); assign libresocsim_csrbank5_en0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd8)); assign libresocsim_csrbank5_update_value0_r = libresocsim_interface5_bank_bus_dat_w[0]; assign libresocsim_csrbank5_update_value0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd9)); assign libresocsim_csrbank5_update_value0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd9)); assign libresocsim_csrbank5_value3_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_value3_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd10)); assign libresocsim_csrbank5_value3_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd10)); assign libresocsim_csrbank5_value2_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_value2_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd11)); assign libresocsim_csrbank5_value2_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd11)); assign libresocsim_csrbank5_value1_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_value1_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd12)); assign libresocsim_csrbank5_value1_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd12)); assign libresocsim_csrbank5_value0_r = libresocsim_interface5_bank_bus_dat_w[7:0]; assign libresocsim_csrbank5_value0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd13)); assign libresocsim_csrbank5_value0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd13)); assign libresocsim_eventmanager_status_r = libresocsim_interface5_bank_bus_dat_w[0]; assign libresocsim_eventmanager_status_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd14)); assign libresocsim_eventmanager_status_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd14)); assign libresocsim_eventmanager_pending_r = libresocsim_interface5_bank_bus_dat_w[0]; assign libresocsim_eventmanager_pending_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd15)); assign libresocsim_eventmanager_pending_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 4'd15)); assign libresocsim_csrbank5_ev_enable0_r = libresocsim_interface5_bank_bus_dat_w[0]; assign libresocsim_csrbank5_ev_enable0_re = ((libresocsim_csrbank5_sel & libresocsim_interface5_bank_bus_we) & (libresocsim_interface5_bank_bus_adr[4:0] == 5'd16)); assign libresocsim_csrbank5_ev_enable0_we = ((libresocsim_csrbank5_sel & (~libresocsim_interface5_bank_bus_we)) & (libresocsim_interface5_bank_bus_adr[4:0] == 5'd16)); assign libresocsim_csrbank5_load3_w = libresocsim_load_storage[31:24]; assign libresocsim_csrbank5_load2_w = libresocsim_load_storage[23:16]; assign libresocsim_csrbank5_load1_w = libresocsim_load_storage[15:8]; assign libresocsim_csrbank5_load0_w = libresocsim_load_storage[7:0]; assign libresocsim_csrbank5_reload3_w = libresocsim_reload_storage[31:24]; assign libresocsim_csrbank5_reload2_w = libresocsim_reload_storage[23:16]; assign libresocsim_csrbank5_reload1_w = libresocsim_reload_storage[15:8]; assign libresocsim_csrbank5_reload0_w = libresocsim_reload_storage[7:0]; assign libresocsim_csrbank5_en0_w = libresocsim_en_storage; assign libresocsim_csrbank5_update_value0_w = libresocsim_update_value_storage; assign libresocsim_csrbank5_value3_w = libresocsim_value_status[31:24]; assign libresocsim_csrbank5_value2_w = libresocsim_value_status[23:16]; assign libresocsim_csrbank5_value1_w = libresocsim_value_status[15:8]; assign libresocsim_csrbank5_value0_w = libresocsim_value_status[7:0]; assign libresocsim_value_we = libresocsim_csrbank5_value0_we; assign libresocsim_csrbank5_ev_enable0_w = libresocsim_eventmanager_storage; assign libresocsim_csrbank6_sel = (libresocsim_interface6_bank_bus_adr[12:9] == 3'd5); assign rxtx_r = libresocsim_interface6_bank_bus_dat_w[7:0]; assign rxtx_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd0)); assign rxtx_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd0)); assign libresocsim_csrbank6_txfull_r = libresocsim_interface6_bank_bus_dat_w[0]; assign libresocsim_csrbank6_txfull_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd1)); assign libresocsim_csrbank6_txfull_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 1'd1)); assign libresocsim_csrbank6_rxempty_r = libresocsim_interface6_bank_bus_dat_w[0]; assign libresocsim_csrbank6_rxempty_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd2)); assign libresocsim_csrbank6_rxempty_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd2)); assign eventmanager_status_r = libresocsim_interface6_bank_bus_dat_w[1:0]; assign eventmanager_status_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd3)); assign eventmanager_status_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 2'd3)); assign eventmanager_pending_r = libresocsim_interface6_bank_bus_dat_w[1:0]; assign eventmanager_pending_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd4)); assign eventmanager_pending_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd4)); assign libresocsim_csrbank6_ev_enable0_r = libresocsim_interface6_bank_bus_dat_w[1:0]; assign libresocsim_csrbank6_ev_enable0_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd5)); assign libresocsim_csrbank6_ev_enable0_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd5)); assign libresocsim_csrbank6_txempty_r = libresocsim_interface6_bank_bus_dat_w[0]; assign libresocsim_csrbank6_txempty_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd6)); assign libresocsim_csrbank6_txempty_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd6)); assign libresocsim_csrbank6_rxfull_r = libresocsim_interface6_bank_bus_dat_w[0]; assign libresocsim_csrbank6_rxfull_re = ((libresocsim_csrbank6_sel & libresocsim_interface6_bank_bus_we) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd7)); assign libresocsim_csrbank6_rxfull_we = ((libresocsim_csrbank6_sel & (~libresocsim_interface6_bank_bus_we)) & (libresocsim_interface6_bank_bus_adr[2:0] == 3'd7)); assign libresocsim_csrbank6_txfull_w = txfull_status; assign txfull_we = libresocsim_csrbank6_txfull_we; assign libresocsim_csrbank6_rxempty_w = rxempty_status; assign rxempty_we = libresocsim_csrbank6_rxempty_we; assign libresocsim_csrbank6_ev_enable0_w = eventmanager_storage[1:0]; assign libresocsim_csrbank6_txempty_w = txempty_status; assign txempty_we = libresocsim_csrbank6_txempty_we; assign libresocsim_csrbank6_rxfull_w = rxfull_status; assign rxfull_we = libresocsim_csrbank6_rxfull_we; assign libresocsim_csrbank7_sel = (libresocsim_interface7_bank_bus_adr[12:9] == 3'd4); assign libresocsim_csrbank7_tuning_word3_r = libresocsim_interface7_bank_bus_dat_w[7:0]; assign libresocsim_csrbank7_tuning_word3_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd0)); assign libresocsim_csrbank7_tuning_word3_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd0)); assign libresocsim_csrbank7_tuning_word2_r = libresocsim_interface7_bank_bus_dat_w[7:0]; assign libresocsim_csrbank7_tuning_word2_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd1)); assign libresocsim_csrbank7_tuning_word2_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 1'd1)); assign libresocsim_csrbank7_tuning_word1_r = libresocsim_interface7_bank_bus_dat_w[7:0]; assign libresocsim_csrbank7_tuning_word1_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd2)); assign libresocsim_csrbank7_tuning_word1_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd2)); assign libresocsim_csrbank7_tuning_word0_r = libresocsim_interface7_bank_bus_dat_w[7:0]; assign libresocsim_csrbank7_tuning_word0_re = ((libresocsim_csrbank7_sel & libresocsim_interface7_bank_bus_we) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd3)); assign libresocsim_csrbank7_tuning_word0_we = ((libresocsim_csrbank7_sel & (~libresocsim_interface7_bank_bus_we)) & (libresocsim_interface7_bank_bus_adr[1:0] == 2'd3)); assign libresocsim_csrbank7_tuning_word3_w = uart_phy_storage[31:24]; assign libresocsim_csrbank7_tuning_word2_w = uart_phy_storage[23:16]; assign libresocsim_csrbank7_tuning_word1_w = uart_phy_storage[15:8]; assign libresocsim_csrbank7_tuning_word0_w = uart_phy_storage[7:0]; assign libresocsim_csr_interconnect_adr = libresocsim_libresocsim_adr; assign libresocsim_csr_interconnect_we = libresocsim_libresocsim_we; assign libresocsim_csr_interconnect_dat_w = libresocsim_libresocsim_dat_w; assign libresocsim_libresocsim_dat_r = libresocsim_csr_interconnect_dat_r; assign libresocsim_interface0_bank_bus_adr = libresocsim_csr_interconnect_adr; assign libresocsim_interface1_bank_bus_adr = libresocsim_csr_interconnect_adr; assign libresocsim_interface2_bank_bus_adr = libresocsim_csr_interconnect_adr; assign libresocsim_interface3_bank_bus_adr = libresocsim_csr_interconnect_adr; assign libresocsim_interface4_bank_bus_adr = libresocsim_csr_interconnect_adr; assign libresocsim_interface5_bank_bus_adr = libresocsim_csr_interconnect_adr; assign libresocsim_interface6_bank_bus_adr = libresocsim_csr_interconnect_adr; assign libresocsim_interface7_bank_bus_adr = libresocsim_csr_interconnect_adr; assign libresocsim_interface0_bank_bus_we = libresocsim_csr_interconnect_we; assign libresocsim_interface1_bank_bus_we = libresocsim_csr_interconnect_we; assign libresocsim_interface2_bank_bus_we = libresocsim_csr_interconnect_we; assign libresocsim_interface3_bank_bus_we = libresocsim_csr_interconnect_we; assign libresocsim_interface4_bank_bus_we = libresocsim_csr_interconnect_we; assign libresocsim_interface5_bank_bus_we = libresocsim_csr_interconnect_we; assign libresocsim_interface6_bank_bus_we = libresocsim_csr_interconnect_we; assign libresocsim_interface7_bank_bus_we = libresocsim_csr_interconnect_we; assign libresocsim_interface0_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; assign libresocsim_interface1_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; assign libresocsim_interface2_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; assign libresocsim_interface3_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; assign libresocsim_interface4_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; assign libresocsim_interface5_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; assign libresocsim_interface6_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; assign libresocsim_interface7_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w; assign libresocsim_csr_interconnect_dat_r = (((((((libresocsim_interface0_bank_bus_dat_r | libresocsim_interface1_bank_bus_dat_r) | libresocsim_interface2_bank_bus_dat_r) | libresocsim_interface3_bank_bus_dat_r) | libresocsim_interface4_bank_bus_dat_r) | libresocsim_interface5_bank_bus_dat_r) | libresocsim_interface6_bank_bus_dat_r) | libresocsim_interface7_bank_bus_dat_r); always @(*) begin rhs_array_muxed0 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[0]; end 1'd1: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[1]; end 2'd2: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[2]; end default: begin rhs_array_muxed0 <= sdram_choose_cmd_valids[3]; end endcase end always @(*) begin rhs_array_muxed1 <= 13'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed1 <= sdram_bankmachine0_cmd_payload_a; end 1'd1: begin rhs_array_muxed1 <= sdram_bankmachine1_cmd_payload_a; end 2'd2: begin rhs_array_muxed1 <= sdram_bankmachine2_cmd_payload_a; end default: begin rhs_array_muxed1 <= sdram_bankmachine3_cmd_payload_a; end endcase end always @(*) begin rhs_array_muxed2 <= 2'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed2 <= sdram_bankmachine0_cmd_payload_ba; end 1'd1: begin rhs_array_muxed2 <= sdram_bankmachine1_cmd_payload_ba; end 2'd2: begin rhs_array_muxed2 <= sdram_bankmachine2_cmd_payload_ba; end default: begin rhs_array_muxed2 <= sdram_bankmachine3_cmd_payload_ba; end endcase end always @(*) begin rhs_array_muxed3 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed3 <= sdram_bankmachine0_cmd_payload_is_read; end 1'd1: begin rhs_array_muxed3 <= sdram_bankmachine1_cmd_payload_is_read; end 2'd2: begin rhs_array_muxed3 <= sdram_bankmachine2_cmd_payload_is_read; end default: begin rhs_array_muxed3 <= sdram_bankmachine3_cmd_payload_is_read; end endcase end always @(*) begin rhs_array_muxed4 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed4 <= sdram_bankmachine0_cmd_payload_is_write; end 1'd1: begin rhs_array_muxed4 <= sdram_bankmachine1_cmd_payload_is_write; end 2'd2: begin rhs_array_muxed4 <= sdram_bankmachine2_cmd_payload_is_write; end default: begin rhs_array_muxed4 <= sdram_bankmachine3_cmd_payload_is_write; end endcase end always @(*) begin rhs_array_muxed5 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin rhs_array_muxed5 <= sdram_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin rhs_array_muxed5 <= sdram_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin rhs_array_muxed5 <= sdram_bankmachine2_cmd_payload_is_cmd; end default: begin rhs_array_muxed5 <= sdram_bankmachine3_cmd_payload_is_cmd; end endcase end always @(*) begin t_array_muxed0 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin t_array_muxed0 <= sdram_bankmachine0_cmd_payload_cas; end 1'd1: begin t_array_muxed0 <= sdram_bankmachine1_cmd_payload_cas; end 2'd2: begin t_array_muxed0 <= sdram_bankmachine2_cmd_payload_cas; end default: begin t_array_muxed0 <= sdram_bankmachine3_cmd_payload_cas; end endcase end always @(*) begin t_array_muxed1 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin t_array_muxed1 <= sdram_bankmachine0_cmd_payload_ras; end 1'd1: begin t_array_muxed1 <= sdram_bankmachine1_cmd_payload_ras; end 2'd2: begin t_array_muxed1 <= sdram_bankmachine2_cmd_payload_ras; end default: begin t_array_muxed1 <= sdram_bankmachine3_cmd_payload_ras; end endcase end always @(*) begin t_array_muxed2 <= 1'd0; case (sdram_choose_cmd_grant) 1'd0: begin t_array_muxed2 <= sdram_bankmachine0_cmd_payload_we; end 1'd1: begin t_array_muxed2 <= sdram_bankmachine1_cmd_payload_we; end 2'd2: begin t_array_muxed2 <= sdram_bankmachine2_cmd_payload_we; end default: begin t_array_muxed2 <= sdram_bankmachine3_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed6 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed6 <= sdram_choose_req_valids[0]; end 1'd1: begin rhs_array_muxed6 <= sdram_choose_req_valids[1]; end 2'd2: begin rhs_array_muxed6 <= sdram_choose_req_valids[2]; end default: begin rhs_array_muxed6 <= sdram_choose_req_valids[3]; end endcase end always @(*) begin rhs_array_muxed7 <= 13'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed7 <= sdram_bankmachine0_cmd_payload_a; end 1'd1: begin rhs_array_muxed7 <= sdram_bankmachine1_cmd_payload_a; end 2'd2: begin rhs_array_muxed7 <= sdram_bankmachine2_cmd_payload_a; end default: begin rhs_array_muxed7 <= sdram_bankmachine3_cmd_payload_a; end endcase end always @(*) begin rhs_array_muxed8 <= 2'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed8 <= sdram_bankmachine0_cmd_payload_ba; end 1'd1: begin rhs_array_muxed8 <= sdram_bankmachine1_cmd_payload_ba; end 2'd2: begin rhs_array_muxed8 <= sdram_bankmachine2_cmd_payload_ba; end default: begin rhs_array_muxed8 <= sdram_bankmachine3_cmd_payload_ba; end endcase end always @(*) begin rhs_array_muxed9 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed9 <= sdram_bankmachine0_cmd_payload_is_read; end 1'd1: begin rhs_array_muxed9 <= sdram_bankmachine1_cmd_payload_is_read; end 2'd2: begin rhs_array_muxed9 <= sdram_bankmachine2_cmd_payload_is_read; end default: begin rhs_array_muxed9 <= sdram_bankmachine3_cmd_payload_is_read; end endcase end always @(*) begin rhs_array_muxed10 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed10 <= sdram_bankmachine0_cmd_payload_is_write; end 1'd1: begin rhs_array_muxed10 <= sdram_bankmachine1_cmd_payload_is_write; end 2'd2: begin rhs_array_muxed10 <= sdram_bankmachine2_cmd_payload_is_write; end default: begin rhs_array_muxed10 <= sdram_bankmachine3_cmd_payload_is_write; end endcase end always @(*) begin rhs_array_muxed11 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin rhs_array_muxed11 <= sdram_bankmachine0_cmd_payload_is_cmd; end 1'd1: begin rhs_array_muxed11 <= sdram_bankmachine1_cmd_payload_is_cmd; end 2'd2: begin rhs_array_muxed11 <= sdram_bankmachine2_cmd_payload_is_cmd; end default: begin rhs_array_muxed11 <= sdram_bankmachine3_cmd_payload_is_cmd; end endcase end always @(*) begin t_array_muxed3 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin t_array_muxed3 <= sdram_bankmachine0_cmd_payload_cas; end 1'd1: begin t_array_muxed3 <= sdram_bankmachine1_cmd_payload_cas; end 2'd2: begin t_array_muxed3 <= sdram_bankmachine2_cmd_payload_cas; end default: begin t_array_muxed3 <= sdram_bankmachine3_cmd_payload_cas; end endcase end always @(*) begin t_array_muxed4 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin t_array_muxed4 <= sdram_bankmachine0_cmd_payload_ras; end 1'd1: begin t_array_muxed4 <= sdram_bankmachine1_cmd_payload_ras; end 2'd2: begin t_array_muxed4 <= sdram_bankmachine2_cmd_payload_ras; end default: begin t_array_muxed4 <= sdram_bankmachine3_cmd_payload_ras; end endcase end always @(*) begin t_array_muxed5 <= 1'd0; case (sdram_choose_req_grant) 1'd0: begin t_array_muxed5 <= sdram_bankmachine0_cmd_payload_we; end 1'd1: begin t_array_muxed5 <= sdram_bankmachine1_cmd_payload_we; end 2'd2: begin t_array_muxed5 <= sdram_bankmachine2_cmd_payload_we; end default: begin t_array_muxed5 <= sdram_bankmachine3_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed12 <= 22'd0; case (subfragments_roundrobin0_grant) default: begin rhs_array_muxed12 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]}; end endcase end always @(*) begin rhs_array_muxed13 <= 1'd0; case (subfragments_roundrobin0_grant) default: begin rhs_array_muxed13 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed14 <= 1'd0; case (subfragments_roundrobin0_grant) default: begin rhs_array_muxed14 <= (((port_cmd_payload_addr[10:9] == 1'd0) & (~(((subfragments_locked0 | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed15 <= 22'd0; case (subfragments_roundrobin1_grant) default: begin rhs_array_muxed15 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]}; end endcase end always @(*) begin rhs_array_muxed16 <= 1'd0; case (subfragments_roundrobin1_grant) default: begin rhs_array_muxed16 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed17 <= 1'd0; case (subfragments_roundrobin1_grant) default: begin rhs_array_muxed17 <= (((port_cmd_payload_addr[10:9] == 1'd1) & (~(((subfragments_locked1 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed18 <= 22'd0; case (subfragments_roundrobin2_grant) default: begin rhs_array_muxed18 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]}; end endcase end always @(*) begin rhs_array_muxed19 <= 1'd0; case (subfragments_roundrobin2_grant) default: begin rhs_array_muxed19 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed20 <= 1'd0; case (subfragments_roundrobin2_grant) default: begin rhs_array_muxed20 <= (((port_cmd_payload_addr[10:9] == 2'd2) & (~(((subfragments_locked2 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank3_lock & (subfragments_roundrobin3_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed21 <= 22'd0; case (subfragments_roundrobin3_grant) default: begin rhs_array_muxed21 <= {port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0]}; end endcase end always @(*) begin rhs_array_muxed22 <= 1'd0; case (subfragments_roundrobin3_grant) default: begin rhs_array_muxed22 <= port_cmd_payload_we; end endcase end always @(*) begin rhs_array_muxed23 <= 1'd0; case (subfragments_roundrobin3_grant) default: begin rhs_array_muxed23 <= (((port_cmd_payload_addr[10:9] == 2'd3) & (~(((subfragments_locked3 | (sdram_interface_bank0_lock & (subfragments_roundrobin0_grant == 1'd0))) | (sdram_interface_bank1_lock & (subfragments_roundrobin1_grant == 1'd0))) | (sdram_interface_bank2_lock & (subfragments_roundrobin2_grant == 1'd0))))) & port_cmd_valid); end endcase end always @(*) begin rhs_array_muxed24 <= 30'd0; case (libresocsim_grant) 1'd0: begin rhs_array_muxed24 <= libresocsim_interface0_converted_interface_adr; end 1'd1: begin rhs_array_muxed24 <= libresocsim_interface1_converted_interface_adr; end default: begin rhs_array_muxed24 <= libresocsim_libresoc_jtag_wb_adr; end endcase end always @(*) begin rhs_array_muxed25 <= 32'd0; case (libresocsim_grant) 1'd0: begin rhs_array_muxed25 <= libresocsim_interface0_converted_interface_dat_w; end 1'd1: begin rhs_array_muxed25 <= libresocsim_interface1_converted_interface_dat_w; end default: begin rhs_array_muxed25 <= libresocsim_libresoc_jtag_wb_dat_w; end endcase end always @(*) begin rhs_array_muxed26 <= 4'd0; case (libresocsim_grant) 1'd0: begin rhs_array_muxed26 <= libresocsim_interface0_converted_interface_sel; end 1'd1: begin rhs_array_muxed26 <= libresocsim_interface1_converted_interface_sel; end default: begin rhs_array_muxed26 <= libresocsim_libresoc_jtag_wb_sel; end endcase end always @(*) begin rhs_array_muxed27 <= 1'd0; case (libresocsim_grant) 1'd0: begin rhs_array_muxed27 <= libresocsim_interface0_converted_interface_cyc; end 1'd1: begin rhs_array_muxed27 <= libresocsim_interface1_converted_interface_cyc; end default: begin rhs_array_muxed27 <= libresocsim_libresoc_jtag_wb_cyc; end endcase end always @(*) begin rhs_array_muxed28 <= 1'd0; case (libresocsim_grant) 1'd0: begin rhs_array_muxed28 <= libresocsim_interface0_converted_interface_stb; end 1'd1: begin rhs_array_muxed28 <= libresocsim_interface1_converted_interface_stb; end default: begin rhs_array_muxed28 <= libresocsim_libresoc_jtag_wb_stb; end endcase end always @(*) begin rhs_array_muxed29 <= 1'd0; case (libresocsim_grant) 1'd0: begin rhs_array_muxed29 <= libresocsim_interface0_converted_interface_we; end 1'd1: begin rhs_array_muxed29 <= libresocsim_interface1_converted_interface_we; end default: begin rhs_array_muxed29 <= libresocsim_libresoc_jtag_wb_we; end endcase end always @(*) begin rhs_array_muxed30 <= 3'd0; case (libresocsim_grant) 1'd0: begin rhs_array_muxed30 <= libresocsim_interface0_converted_interface_cti; end 1'd1: begin rhs_array_muxed30 <= libresocsim_interface1_converted_interface_cti; end default: begin rhs_array_muxed30 <= libresocsim_libresoc_jtag_wb_cti; end endcase end always @(*) begin rhs_array_muxed31 <= 2'd0; case (libresocsim_grant) 1'd0: begin rhs_array_muxed31 <= libresocsim_interface0_converted_interface_bte; end 1'd1: begin rhs_array_muxed31 <= libresocsim_interface1_converted_interface_bte; end default: begin rhs_array_muxed31 <= libresocsim_libresoc_jtag_wb_bte; end endcase end always @(*) begin array_muxed0 <= 2'd0; case (sdram_steerer_sel) 1'd0: begin array_muxed0 <= sdram_nop_ba[1:0]; end 1'd1: begin array_muxed0 <= sdram_choose_req_cmd_payload_ba[1:0]; end 2'd2: begin array_muxed0 <= sdram_choose_req_cmd_payload_ba[1:0]; end default: begin array_muxed0 <= sdram_cmd_payload_ba[1:0]; end endcase end always @(*) begin array_muxed1 <= 13'd0; case (sdram_steerer_sel) 1'd0: begin array_muxed1 <= sdram_nop_a; end 1'd1: begin array_muxed1 <= sdram_choose_req_cmd_payload_a; end 2'd2: begin array_muxed1 <= sdram_choose_req_cmd_payload_a; end default: begin array_muxed1 <= sdram_cmd_payload_a; end endcase end always @(*) begin array_muxed2 <= 1'd0; case (sdram_steerer_sel) 1'd0: begin array_muxed2 <= 1'd0; end 1'd1: begin array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); end 2'd2: begin array_muxed2 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_cas); end default: begin array_muxed2 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_cas); end endcase end always @(*) begin array_muxed3 <= 1'd0; case (sdram_steerer_sel) 1'd0: begin array_muxed3 <= 1'd0; end 1'd1: begin array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); end 2'd2: begin array_muxed3 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_ras); end default: begin array_muxed3 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_ras); end endcase end always @(*) begin array_muxed4 <= 1'd0; case (sdram_steerer_sel) 1'd0: begin array_muxed4 <= 1'd0; end 1'd1: begin array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); end 2'd2: begin array_muxed4 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_we); end default: begin array_muxed4 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_we); end endcase end always @(*) begin array_muxed5 <= 1'd0; case (sdram_steerer_sel) 1'd0: begin array_muxed5 <= 1'd0; end 1'd1: begin array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); end 2'd2: begin array_muxed5 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_read); end default: begin array_muxed5 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_read); end endcase end always @(*) begin array_muxed6 <= 1'd0; case (sdram_steerer_sel) 1'd0: begin array_muxed6 <= 1'd0; end 1'd1: begin array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); end 2'd2: begin array_muxed6 <= ((sdram_choose_req_cmd_valid & sdram_choose_req_cmd_ready) & sdram_choose_req_cmd_payload_is_write); end default: begin array_muxed6 <= ((sdram_cmd_valid & sdram_cmd_ready) & sdram_cmd_payload_is_write); end endcase end assign sdrio_clk = sys_clk_1; assign sdrio_clk_1 = sys_clk_1; assign sdrio_clk_2 = sys_clk_1; assign sdrio_clk_3 = sys_clk_1; assign sdrio_clk_4 = sys_clk_1; assign sdrio_clk_5 = sys_clk_1; assign sdrio_clk_6 = sys_clk_1; assign sdrio_clk_7 = sys_clk_1; assign sdrio_clk_8 = sys_clk_1; assign sdrio_clk_9 = sys_clk_1; assign sdrio_clk_10 = sys_clk_1; assign sdrio_clk_11 = sys_clk_1; assign sdrio_clk_12 = sys_clk_1; assign sdrio_clk_13 = sys_clk_1; assign sdrio_clk_14 = sys_clk_1; assign sdrio_clk_15 = sys_clk_1; assign sdrio_clk_16 = sys_clk_1; assign sdrio_clk_17 = sys_clk_1; assign sdrio_clk_18 = sys_clk_1; assign sdrio_clk_19 = sys_clk_1; assign sdrio_clk_20 = sys_clk_1; assign sdrio_clk_21 = sys_clk_1; assign sdrio_clk_22 = sys_clk_1; assign sdrio_clk_23 = sys_clk_1; assign sdrio_clk_24 = sys_clk_1; assign sdrio_clk_25 = sys_clk_1; assign sdrio_clk_26 = sys_clk_1; assign sdrio_clk_27 = sys_clk_1; assign sdrio_clk_28 = sys_clk_1; assign sdrio_clk_29 = sys_clk_1; assign sdrio_clk_30 = sys_clk_1; assign sdrio_clk_31 = sys_clk_1; assign sdrio_clk_32 = sys_clk_1; assign sdrio_clk_33 = sys_clk_1; assign sdrio_clk_34 = sys_clk_1; assign sdrio_clk_35 = sys_clk_1; assign sdrio_clk_36 = sys_clk_1; assign sdrio_clk_37 = sys_clk_1; assign sdrio_clk_38 = sys_clk_1; assign sdrio_clk_39 = sys_clk_1; assign sdrio_clk_40 = sys_clk_1; assign sdrio_clk_41 = sys_clk_1; assign sdrio_clk_42 = sys_clk_1; assign sdrio_clk_43 = sys_clk_1; assign sdrio_clk_44 = sys_clk_1; assign sdrio_clk_45 = sys_clk_1; assign sdrio_clk_46 = sys_clk_1; assign sdrio_clk_47 = sys_clk_1; assign sdrio_clk_48 = sys_clk_1; assign sdrio_clk_49 = sys_clk_1; assign sdrio_clk_50 = sys_clk_1; assign sdrio_clk_51 = sys_clk_1; assign sdrio_clk_52 = sys_clk_1; assign sdrio_clk_53 = sys_clk_1; assign sdrio_clk_54 = sys_clk_1; assign sdrio_clk_55 = sys_clk_1; assign sdrio_clk_56 = sys_clk_1; assign sdrio_clk_57 = sys_clk_1; assign sdrio_clk_58 = sys_clk_1; assign sdrio_clk_59 = sys_clk_1; assign sdrio_clk_60 = sys_clk_1; assign sdrio_clk_61 = sys_clk_1; assign sdrio_clk_62 = sys_clk_1; assign sdrio_clk_63 = sys_clk_1; assign sdrio_clk_64 = sys_clk_1; assign sdrio_clk_65 = sys_clk_1; assign sdrio_clk_66 = sys_clk_1; assign sdrio_clk_67 = sys_clk_1; assign sdrio_clk_68 = sys_clk_1; assign sdrio_clk_69 = sys_clk_1; assign sdrio_clk_70 = sys_clk_1; assign uart_phy_rx = regs1; assign sdrio_clk_71 = sys_clk_1; assign sdrio_clk_72 = sys_clk_1; assign sdrio_clk_73 = sys_clk_1; assign sdrio_clk_74 = sys_clk_1; assign sdrio_clk_75 = sys_clk_1; assign sdrio_clk_76 = sys_clk_1; assign sdrio_clk_77 = sys_clk_1; assign sdrio_clk_78 = sys_clk_1; assign sdrio_clk_79 = sys_clk_1; assign sdrio_clk_80 = sys_clk_1; assign sdrio_clk_81 = sys_clk_1; assign sdrio_clk_82 = sys_clk_1; assign sdrio_clk_83 = sys_clk_1; assign sdrio_clk_84 = sys_clk_1; assign sdrio_clk_85 = sys_clk_1; assign sdrio_clk_86 = sys_clk_1; assign sdrio_clk_87 = sys_clk_1; assign sdrio_clk_88 = sys_clk_1; assign sdrio_clk_89 = sys_clk_1; assign sdrio_clk_90 = sys_clk_1; assign sdrio_clk_91 = sys_clk_1; assign sdrio_clk_92 = sys_clk_1; assign sdrio_clk_93 = sys_clk_1; assign sdrio_clk_94 = sys_clk_1; assign sdrio_clk_95 = sys_clk_1; assign sdrio_clk_96 = sys_clk_1; assign sdrio_clk_97 = sys_clk_1; assign sdrio_clk_98 = sys_clk_1; assign sdrio_clk_99 = sys_clk_1; assign sdrio_clk_100 = sys_clk_1; assign sdrio_clk_101 = sys_clk_1; assign sdrio_clk_102 = sys_clk_1; assign sdrio_clk_103 = sys_clk_1; assign sdrio_clk_104 = sys_clk_1; assign sdrio_clk_105 = sys_clk_1; assign sdrio_clk_106 = sys_clk_1; assign sdrio_clk_107 = sys_clk_1; assign sdrio_clk_108 = sys_clk_1; assign sdrio_clk_109 = sys_clk_1; assign sdrio_clk_110 = sys_clk_1; assign sdrio_clk_111 = sys_clk_1; assign sdrio_clk_112 = sys_clk_1; assign sdrio_clk_113 = sys_clk_1; assign sdrio_clk_114 = sys_clk_1; assign sdrio_clk_115 = sys_clk_1; assign sdrio_clk_116 = sys_clk_1; assign sdrio_clk_117 = sys_clk_1; assign sdrio_clk_118 = sys_clk_1; always @(posedge por_clk) begin int_rst <= sys_rst; end always @(posedge sdrio_clk) begin libresocsim_libresoc_constraintmanager_sdram_a[0] <= dfi_p0_address[0]; libresocsim_libresoc_constraintmanager_sdram_a[1] <= dfi_p0_address[1]; libresocsim_libresoc_constraintmanager_sdram_a[2] <= dfi_p0_address[2]; libresocsim_libresoc_constraintmanager_sdram_a[3] <= dfi_p0_address[3]; libresocsim_libresoc_constraintmanager_sdram_a[4] <= dfi_p0_address[4]; libresocsim_libresoc_constraintmanager_sdram_a[5] <= dfi_p0_address[5]; libresocsim_libresoc_constraintmanager_sdram_a[6] <= dfi_p0_address[6]; libresocsim_libresoc_constraintmanager_sdram_a[7] <= dfi_p0_address[7]; libresocsim_libresoc_constraintmanager_sdram_a[8] <= dfi_p0_address[8]; libresocsim_libresoc_constraintmanager_sdram_a[9] <= dfi_p0_address[9]; libresocsim_libresoc_constraintmanager_sdram_a[10] <= dfi_p0_address[10]; libresocsim_libresoc_constraintmanager_sdram_a[11] <= dfi_p0_address[11]; libresocsim_libresoc_constraintmanager_sdram_a[12] <= dfi_p0_address[12]; libresocsim_libresoc_constraintmanager_sdram_ba[0] <= dfi_p0_bank[0]; libresocsim_libresoc_constraintmanager_sdram_ba[1] <= dfi_p0_bank[1]; libresocsim_libresoc_constraintmanager_sdram_cas_n <= dfi_p0_cas_n; libresocsim_libresoc_constraintmanager_sdram_ras_n <= dfi_p0_ras_n; libresocsim_libresoc_constraintmanager_sdram_we_n <= dfi_p0_we_n; libresocsim_libresoc_constraintmanager_sdram_cke <= dfi_p0_cke; libresocsim_libresoc_constraintmanager_sdram_cs_n <= dfi_p0_cs_n; libresocsim_libresoc_constraintmanager_sdram_dq_oe[0] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[0] <= dfi_p0_wrdata[0]; dfi_p0_rddata[0] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[0]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[1] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[1] <= dfi_p0_wrdata[1]; dfi_p0_rddata[1] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[1]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[2] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[2] <= dfi_p0_wrdata[2]; dfi_p0_rddata[2] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[2]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[3] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[3] <= dfi_p0_wrdata[3]; dfi_p0_rddata[3] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[3]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[4] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[4] <= dfi_p0_wrdata[4]; dfi_p0_rddata[4] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[4]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[5] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[5] <= dfi_p0_wrdata[5]; dfi_p0_rddata[5] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[5]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[6] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[6] <= dfi_p0_wrdata[6]; dfi_p0_rddata[6] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[6]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[7] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[7] <= dfi_p0_wrdata[7]; dfi_p0_rddata[7] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[7]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[8] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[8] <= dfi_p0_wrdata[8]; dfi_p0_rddata[8] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[8]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[9] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[9] <= dfi_p0_wrdata[9]; dfi_p0_rddata[9] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[9]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[10] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[10] <= dfi_p0_wrdata[10]; dfi_p0_rddata[10] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[10]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[11] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[11] <= dfi_p0_wrdata[11]; dfi_p0_rddata[11] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[11]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[12] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[12] <= dfi_p0_wrdata[12]; dfi_p0_rddata[12] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[12]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[13] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[13] <= dfi_p0_wrdata[13]; dfi_p0_rddata[13] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[13]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[14] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[14] <= dfi_p0_wrdata[14]; dfi_p0_rddata[14] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[14]; libresocsim_libresoc_constraintmanager_sdram_dq_oe[15] <= dfi_p0_wrdata_en; libresocsim_libresoc_constraintmanager_sdram_dq_o[15] <= dfi_p0_wrdata[15]; dfi_p0_rddata[15] <= libresocsim_libresoc_constraintmanager_sdram_dq_i[15]; libresocsim_libresoc_constraintmanager_sdram_dm[0] <= (dfi_p0_wrdata_en & dfi_p0_wrdata_mask[0]); libresocsim_libresoc_constraintmanager_sdram_dm[1] <= (dfi_p0_wrdata_en & dfi_p0_wrdata_mask[1]); libresocsim_libresoc_constraintmanager_sdram_clock <= sys_clk_1; gpio0_pads_gpio0oe[0] <= gpio0_oe_storage[0]; gpio0_pads_gpio0o[0] <= gpio0_out_storage[0]; gpio0_status[0] <= gpio0_pads_gpio0i[0]; gpio0_pads_gpio0oe[1] <= gpio0_oe_storage[1]; gpio0_pads_gpio0o[1] <= gpio0_out_storage[1]; gpio0_status[1] <= gpio0_pads_gpio0i[1]; gpio0_pads_gpio0oe[2] <= gpio0_oe_storage[2]; gpio0_pads_gpio0o[2] <= gpio0_out_storage[2]; gpio0_status[2] <= gpio0_pads_gpio0i[2]; gpio0_pads_gpio0oe[3] <= gpio0_oe_storage[3]; gpio0_pads_gpio0o[3] <= gpio0_out_storage[3]; gpio0_status[3] <= gpio0_pads_gpio0i[3]; gpio0_pads_gpio0oe[4] <= gpio0_oe_storage[4]; gpio0_pads_gpio0o[4] <= gpio0_out_storage[4]; gpio0_status[4] <= gpio0_pads_gpio0i[4]; gpio0_pads_gpio0oe[5] <= gpio0_oe_storage[5]; gpio0_pads_gpio0o[5] <= gpio0_out_storage[5]; gpio0_status[5] <= gpio0_pads_gpio0i[5]; gpio0_pads_gpio0oe[6] <= gpio0_oe_storage[6]; gpio0_pads_gpio0o[6] <= gpio0_out_storage[6]; gpio0_status[6] <= gpio0_pads_gpio0i[6]; gpio0_pads_gpio0oe[7] <= gpio0_oe_storage[7]; gpio0_pads_gpio0o[7] <= gpio0_out_storage[7]; gpio0_status[7] <= gpio0_pads_gpio0i[7]; gpio1_pads_gpio1oe[0] <= gpio1_oe_storage[0]; gpio1_pads_gpio1o[0] <= gpio1_out_storage[0]; gpio1_status[0] <= gpio1_pads_gpio1i[0]; gpio1_pads_gpio1oe[1] <= gpio1_oe_storage[1]; gpio1_pads_gpio1o[1] <= gpio1_out_storage[1]; gpio1_status[1] <= gpio1_pads_gpio1i[1]; gpio1_pads_gpio1oe[2] <= gpio1_oe_storage[2]; gpio1_pads_gpio1o[2] <= gpio1_out_storage[2]; gpio1_status[2] <= gpio1_pads_gpio1i[2]; gpio1_pads_gpio1oe[3] <= gpio1_oe_storage[3]; gpio1_pads_gpio1o[3] <= gpio1_out_storage[3]; gpio1_status[3] <= gpio1_pads_gpio1i[3]; gpio1_pads_gpio1oe[4] <= gpio1_oe_storage[4]; gpio1_pads_gpio1o[4] <= gpio1_out_storage[4]; gpio1_status[4] <= gpio1_pads_gpio1i[4]; gpio1_pads_gpio1oe[5] <= gpio1_oe_storage[5]; gpio1_pads_gpio1o[5] <= gpio1_out_storage[5]; gpio1_status[5] <= gpio1_pads_gpio1i[5]; gpio1_pads_gpio1oe[6] <= gpio1_oe_storage[6]; gpio1_pads_gpio1o[6] <= gpio1_out_storage[6]; gpio1_status[6] <= gpio1_pads_gpio1i[6]; gpio1_pads_gpio1oe[7] <= gpio1_oe_storage[7]; gpio1_pads_gpio1o[7] <= gpio1_out_storage[7]; gpio1_status[7] <= gpio1_pads_gpio1i[7]; end always @(posedge sys_clk_1) begin dummy[0] <= (nc_1[0] | libresocsim_libresoc_interrupt[0]); dummy[1] <= (nc_1[1] | libresocsim_libresoc_interrupt[0]); dummy[2] <= (nc_1[2] | libresocsim_libresoc_interrupt[0]); dummy[3] <= (nc_1[3] | libresocsim_libresoc_interrupt[0]); dummy[4] <= (nc_1[4] | libresocsim_libresoc_interrupt[0]); dummy[5] <= (nc_1[5] | libresocsim_libresoc_interrupt[0]); dummy[6] <= (nc_1[6] | libresocsim_libresoc_interrupt[0]); dummy[7] <= (nc_1[7] | libresocsim_libresoc_interrupt[0]); dummy[8] <= (nc_1[8] | libresocsim_libresoc_interrupt[0]); dummy[9] <= (nc_1[9] | libresocsim_libresoc_interrupt[0]); dummy[10] <= (nc_1[10] | libresocsim_libresoc_interrupt[0]); dummy[11] <= (nc_1[11] | libresocsim_libresoc_interrupt[0]); dummy[12] <= (nc_1[12] | libresocsim_libresoc_interrupt[0]); dummy[13] <= (nc_1[13] | libresocsim_libresoc_interrupt[0]); dummy[14] <= (nc_1[14] | libresocsim_libresoc_interrupt[0]); dummy[15] <= (nc_1[15] | libresocsim_libresoc_interrupt[0]); dummy[16] <= (nc_1[16] | libresocsim_libresoc_interrupt[0]); dummy[17] <= (nc_1[17] | libresocsim_libresoc_interrupt[0]); dummy[18] <= (nc_1[18] | libresocsim_libresoc_interrupt[0]); dummy[19] <= (nc_1[19] | libresocsim_libresoc_interrupt[0]); dummy[20] <= (nc_1[20] | libresocsim_libresoc_interrupt[0]); dummy[21] <= (nc_1[21] | libresocsim_libresoc_interrupt[0]); dummy[22] <= (nc_1[22] | libresocsim_libresoc_interrupt[0]); dummy[23] <= (nc_1[23] | libresocsim_libresoc_interrupt[0]); dummy[24] <= (nc_1[24] | libresocsim_libresoc_interrupt[0]); dummy[25] <= (nc_1[25] | libresocsim_libresoc_interrupt[0]); dummy[26] <= (nc_1[26] | libresocsim_libresoc_interrupt[0]); dummy[27] <= (nc_1[27] | libresocsim_libresoc_interrupt[0]); dummy[28] <= (nc_1[28] | libresocsim_libresoc_interrupt[0]); dummy[29] <= (nc_1[29] | libresocsim_libresoc_interrupt[0]); dummy[30] <= (nc_1[30] | libresocsim_libresoc_interrupt[0]); dummy[31] <= (nc_1[31] | libresocsim_libresoc_interrupt[0]); dummy[32] <= (nc_1[32] | libresocsim_libresoc_interrupt[0]); dummy[33] <= (nc_1[33] | libresocsim_libresoc_interrupt[0]); dummy[34] <= (nc_1[34] | libresocsim_libresoc_interrupt[0]); dummy[35] <= (nc_1[35] | libresocsim_libresoc_interrupt[0]); dummy[36] <= (nc_1[36] | libresocsim_libresoc_interrupt[0]); dummy[37] <= (nc_1[37] | libresocsim_libresoc_interrupt[0]); dummy[38] <= (nc_1[38] | libresocsim_libresoc_interrupt[0]); dummy[39] <= (nc_1[39] | libresocsim_libresoc_interrupt[0]); if ((libresocsim_interface0_converted_interface_ack | libresocsim_converter0_skip)) begin libresocsim_converter0_dat_r <= libresocsim_libresoc_ibus_dat_r; end subfragments_converter0_state <= subfragments_converter0_next_state; if (libresocsim_converter0_counter_subfragments_converter0_next_value_ce) begin libresocsim_converter0_counter <= libresocsim_converter0_counter_subfragments_converter0_next_value; end if (libresocsim_converter0_reset) begin libresocsim_converter0_counter <= 1'd0; subfragments_converter0_state <= 1'd0; end if ((libresocsim_interface1_converted_interface_ack | libresocsim_converter1_skip)) begin libresocsim_converter1_dat_r <= libresocsim_libresoc_dbus_dat_r; end subfragments_converter1_state <= subfragments_converter1_next_state; if (libresocsim_converter1_counter_subfragments_converter1_next_value_ce) begin libresocsim_converter1_counter <= libresocsim_converter1_counter_subfragments_converter1_next_value; end if (libresocsim_converter1_reset) begin libresocsim_converter1_counter <= 1'd0; subfragments_converter1_state <= 1'd0; end if ((libresocsim_bus_errors != 32'd4294967295)) begin if (libresocsim_bus_error) begin libresocsim_bus_errors <= (libresocsim_bus_errors + 1'd1); end end libresocsim_ram_bus_ack <= 1'd0; if (((libresocsim_ram_bus_cyc & libresocsim_ram_bus_stb) & (~libresocsim_ram_bus_ack))) begin libresocsim_ram_bus_ack <= 1'd1; end if (libresocsim_en_storage) begin if ((libresocsim_value == 1'd0)) begin libresocsim_value <= libresocsim_reload_storage; end else begin libresocsim_value <= (libresocsim_value - 1'd1); end end else begin libresocsim_value <= libresocsim_load_storage; end if (libresocsim_update_value_re) begin libresocsim_value_status <= libresocsim_value; end if (libresocsim_zero_clear) begin libresocsim_zero_pending <= 1'd0; end libresocsim_zero_old_trigger <= libresocsim_zero_trigger; if (((~libresocsim_zero_trigger) & libresocsim_zero_old_trigger)) begin libresocsim_zero_pending <= 1'd1; end ram_bus_ram_bus_ack <= 1'd0; if (((ram_bus_ram_bus_cyc & ram_bus_ram_bus_stb) & (~ram_bus_ram_bus_ack))) begin ram_bus_ram_bus_ack <= 1'd1; end rddata_en <= {rddata_en, dfi_p0_rddata_en}; dfi_p0_rddata_valid <= rddata_en[2]; if (sdram_inti_p0_rddata_valid) begin sdram_status <= sdram_inti_p0_rddata; end if ((sdram_timer_wait & (~sdram_timer_done0))) begin sdram_timer_count1 <= (sdram_timer_count1 - 1'd1); end else begin sdram_timer_count1 <= 10'd781; end sdram_postponer_req_o <= 1'd0; if (sdram_postponer_req_i) begin sdram_postponer_count <= (sdram_postponer_count - 1'd1); if ((sdram_postponer_count == 1'd0)) begin sdram_postponer_count <= 1'd0; sdram_postponer_req_o <= 1'd1; end end if (sdram_sequencer_start0) begin sdram_sequencer_count <= 1'd0; end else begin if (sdram_sequencer_done1) begin if ((sdram_sequencer_count != 1'd0)) begin sdram_sequencer_count <= (sdram_sequencer_count - 1'd1); end end end sdram_cmd_payload_a <= 1'd0; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd0; sdram_cmd_payload_ras <= 1'd0; sdram_cmd_payload_we <= 1'd0; sdram_sequencer_done1 <= 1'd0; if ((sdram_sequencer_start1 & (sdram_sequencer_counter == 1'd0))) begin sdram_cmd_payload_a <= 11'd1024; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd0; sdram_cmd_payload_ras <= 1'd1; sdram_cmd_payload_we <= 1'd1; end if ((sdram_sequencer_counter == 2'd2)) begin sdram_cmd_payload_a <= 1'd0; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd1; sdram_cmd_payload_ras <= 1'd1; sdram_cmd_payload_we <= 1'd0; end if ((sdram_sequencer_counter == 4'd8)) begin sdram_cmd_payload_a <= 1'd0; sdram_cmd_payload_ba <= 1'd0; sdram_cmd_payload_cas <= 1'd0; sdram_cmd_payload_ras <= 1'd0; sdram_cmd_payload_we <= 1'd0; sdram_sequencer_done1 <= 1'd1; end if ((sdram_sequencer_counter == 4'd8)) begin sdram_sequencer_counter <= 1'd0; end else begin if ((sdram_sequencer_counter != 1'd0)) begin sdram_sequencer_counter <= (sdram_sequencer_counter + 1'd1); end else begin if (sdram_sequencer_start1) begin sdram_sequencer_counter <= 1'd1; end end end subfragments_refresher_state <= subfragments_refresher_next_state; if (sdram_bankmachine0_row_close) begin sdram_bankmachine0_row_opened <= 1'd0; end else begin if (sdram_bankmachine0_row_open) begin sdram_bankmachine0_row_opened <= 1'd1; sdram_bankmachine0_row <= sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9]; end end if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin sdram_bankmachine0_cmd_buffer_lookahead_produce <= (sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin sdram_bankmachine0_cmd_buffer_lookahead_consume <= (sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin sdram_bankmachine0_cmd_buffer_lookahead_level <= (sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine0_cmd_buffer_source_valid) | sdram_bankmachine0_cmd_buffer_source_ready)) begin sdram_bankmachine0_cmd_buffer_source_valid <= sdram_bankmachine0_cmd_buffer_sink_valid; sdram_bankmachine0_cmd_buffer_source_first <= sdram_bankmachine0_cmd_buffer_sink_first; sdram_bankmachine0_cmd_buffer_source_last <= sdram_bankmachine0_cmd_buffer_sink_last; sdram_bankmachine0_cmd_buffer_source_payload_we <= sdram_bankmachine0_cmd_buffer_sink_payload_we; sdram_bankmachine0_cmd_buffer_source_payload_addr <= sdram_bankmachine0_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine0_twtpcon_valid) begin sdram_bankmachine0_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine0_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine0_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine0_twtpcon_ready)) begin sdram_bankmachine0_twtpcon_count <= (sdram_bankmachine0_twtpcon_count - 1'd1); if ((sdram_bankmachine0_twtpcon_count == 1'd1)) begin sdram_bankmachine0_twtpcon_ready <= 1'd1; end end end subfragments_bankmachine0_state <= subfragments_bankmachine0_next_state; if (sdram_bankmachine1_row_close) begin sdram_bankmachine1_row_opened <= 1'd0; end else begin if (sdram_bankmachine1_row_open) begin sdram_bankmachine1_row_opened <= 1'd1; sdram_bankmachine1_row <= sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9]; end end if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin sdram_bankmachine1_cmd_buffer_lookahead_produce <= (sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin sdram_bankmachine1_cmd_buffer_lookahead_consume <= (sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin sdram_bankmachine1_cmd_buffer_lookahead_level <= (sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine1_cmd_buffer_source_valid) | sdram_bankmachine1_cmd_buffer_source_ready)) begin sdram_bankmachine1_cmd_buffer_source_valid <= sdram_bankmachine1_cmd_buffer_sink_valid; sdram_bankmachine1_cmd_buffer_source_first <= sdram_bankmachine1_cmd_buffer_sink_first; sdram_bankmachine1_cmd_buffer_source_last <= sdram_bankmachine1_cmd_buffer_sink_last; sdram_bankmachine1_cmd_buffer_source_payload_we <= sdram_bankmachine1_cmd_buffer_sink_payload_we; sdram_bankmachine1_cmd_buffer_source_payload_addr <= sdram_bankmachine1_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine1_twtpcon_valid) begin sdram_bankmachine1_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine1_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine1_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine1_twtpcon_ready)) begin sdram_bankmachine1_twtpcon_count <= (sdram_bankmachine1_twtpcon_count - 1'd1); if ((sdram_bankmachine1_twtpcon_count == 1'd1)) begin sdram_bankmachine1_twtpcon_ready <= 1'd1; end end end subfragments_bankmachine1_state <= subfragments_bankmachine1_next_state; if (sdram_bankmachine2_row_close) begin sdram_bankmachine2_row_opened <= 1'd0; end else begin if (sdram_bankmachine2_row_open) begin sdram_bankmachine2_row_opened <= 1'd1; sdram_bankmachine2_row <= sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9]; end end if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin sdram_bankmachine2_cmd_buffer_lookahead_produce <= (sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin sdram_bankmachine2_cmd_buffer_lookahead_consume <= (sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin sdram_bankmachine2_cmd_buffer_lookahead_level <= (sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine2_cmd_buffer_source_valid) | sdram_bankmachine2_cmd_buffer_source_ready)) begin sdram_bankmachine2_cmd_buffer_source_valid <= sdram_bankmachine2_cmd_buffer_sink_valid; sdram_bankmachine2_cmd_buffer_source_first <= sdram_bankmachine2_cmd_buffer_sink_first; sdram_bankmachine2_cmd_buffer_source_last <= sdram_bankmachine2_cmd_buffer_sink_last; sdram_bankmachine2_cmd_buffer_source_payload_we <= sdram_bankmachine2_cmd_buffer_sink_payload_we; sdram_bankmachine2_cmd_buffer_source_payload_addr <= sdram_bankmachine2_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine2_twtpcon_valid) begin sdram_bankmachine2_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine2_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine2_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine2_twtpcon_ready)) begin sdram_bankmachine2_twtpcon_count <= (sdram_bankmachine2_twtpcon_count - 1'd1); if ((sdram_bankmachine2_twtpcon_count == 1'd1)) begin sdram_bankmachine2_twtpcon_ready <= 1'd1; end end end subfragments_bankmachine2_state <= subfragments_bankmachine2_next_state; if (sdram_bankmachine3_row_close) begin sdram_bankmachine3_row_opened <= 1'd0; end else begin if (sdram_bankmachine3_row_open) begin sdram_bankmachine3_row_opened <= 1'd1; sdram_bankmachine3_row <= sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9]; end end if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin sdram_bankmachine3_cmd_buffer_lookahead_produce <= (sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); end if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin sdram_bankmachine3_cmd_buffer_lookahead_consume <= (sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); end if (((sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin if ((~sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1); end end else begin if (sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin sdram_bankmachine3_cmd_buffer_lookahead_level <= (sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1); end end if (((~sdram_bankmachine3_cmd_buffer_source_valid) | sdram_bankmachine3_cmd_buffer_source_ready)) begin sdram_bankmachine3_cmd_buffer_source_valid <= sdram_bankmachine3_cmd_buffer_sink_valid; sdram_bankmachine3_cmd_buffer_source_first <= sdram_bankmachine3_cmd_buffer_sink_first; sdram_bankmachine3_cmd_buffer_source_last <= sdram_bankmachine3_cmd_buffer_sink_last; sdram_bankmachine3_cmd_buffer_source_payload_we <= sdram_bankmachine3_cmd_buffer_sink_payload_we; sdram_bankmachine3_cmd_buffer_source_payload_addr <= sdram_bankmachine3_cmd_buffer_sink_payload_addr; end if (sdram_bankmachine3_twtpcon_valid) begin sdram_bankmachine3_twtpcon_count <= 3'd4; if (1'd0) begin sdram_bankmachine3_twtpcon_ready <= 1'd1; end else begin sdram_bankmachine3_twtpcon_ready <= 1'd0; end end else begin if ((~sdram_bankmachine3_twtpcon_ready)) begin sdram_bankmachine3_twtpcon_count <= (sdram_bankmachine3_twtpcon_count - 1'd1); if ((sdram_bankmachine3_twtpcon_count == 1'd1)) begin sdram_bankmachine3_twtpcon_ready <= 1'd1; end end end subfragments_bankmachine3_state <= subfragments_bankmachine3_next_state; if ((~sdram_en0)) begin sdram_time0 <= 5'd31; end else begin if ((~sdram_max_time0)) begin sdram_time0 <= (sdram_time0 - 1'd1); end end if ((~sdram_en1)) begin sdram_time1 <= 4'd15; end else begin if ((~sdram_max_time1)) begin sdram_time1 <= (sdram_time1 - 1'd1); end end if (sdram_choose_cmd_ce) begin case (sdram_choose_cmd_grant) 1'd0: begin if (sdram_choose_cmd_request[1]) begin sdram_choose_cmd_grant <= 1'd1; end else begin if (sdram_choose_cmd_request[2]) begin sdram_choose_cmd_grant <= 2'd2; end else begin if (sdram_choose_cmd_request[3]) begin sdram_choose_cmd_grant <= 2'd3; end end end end 1'd1: begin if (sdram_choose_cmd_request[2]) begin sdram_choose_cmd_grant <= 2'd2; end else begin if (sdram_choose_cmd_request[3]) begin sdram_choose_cmd_grant <= 2'd3; end else begin if (sdram_choose_cmd_request[0]) begin sdram_choose_cmd_grant <= 1'd0; end end end end 2'd2: begin if (sdram_choose_cmd_request[3]) begin sdram_choose_cmd_grant <= 2'd3; end else begin if (sdram_choose_cmd_request[0]) begin sdram_choose_cmd_grant <= 1'd0; end else begin if (sdram_choose_cmd_request[1]) begin sdram_choose_cmd_grant <= 1'd1; end end end end 2'd3: begin if (sdram_choose_cmd_request[0]) begin sdram_choose_cmd_grant <= 1'd0; end else begin if (sdram_choose_cmd_request[1]) begin sdram_choose_cmd_grant <= 1'd1; end else begin if (sdram_choose_cmd_request[2]) begin sdram_choose_cmd_grant <= 2'd2; end end end end endcase end if (sdram_choose_req_ce) begin case (sdram_choose_req_grant) 1'd0: begin if (sdram_choose_req_request[1]) begin sdram_choose_req_grant <= 1'd1; end else begin if (sdram_choose_req_request[2]) begin sdram_choose_req_grant <= 2'd2; end else begin if (sdram_choose_req_request[3]) begin sdram_choose_req_grant <= 2'd3; end end end end 1'd1: begin if (sdram_choose_req_request[2]) begin sdram_choose_req_grant <= 2'd2; end else begin if (sdram_choose_req_request[3]) begin sdram_choose_req_grant <= 2'd3; end else begin if (sdram_choose_req_request[0]) begin sdram_choose_req_grant <= 1'd0; end end end end 2'd2: begin if (sdram_choose_req_request[3]) begin sdram_choose_req_grant <= 2'd3; end else begin if (sdram_choose_req_request[0]) begin sdram_choose_req_grant <= 1'd0; end else begin if (sdram_choose_req_request[1]) begin sdram_choose_req_grant <= 1'd1; end end end end 2'd3: begin if (sdram_choose_req_request[0]) begin sdram_choose_req_grant <= 1'd0; end else begin if (sdram_choose_req_request[1]) begin sdram_choose_req_grant <= 1'd1; end else begin if (sdram_choose_req_request[2]) begin sdram_choose_req_grant <= 2'd2; end end end end endcase end sdram_dfi_p0_cs_n <= 1'd0; sdram_dfi_p0_bank <= array_muxed0; sdram_dfi_p0_address <= array_muxed1; sdram_dfi_p0_cas_n <= (~array_muxed2); sdram_dfi_p0_ras_n <= (~array_muxed3); sdram_dfi_p0_we_n <= (~array_muxed4); sdram_dfi_p0_rddata_en <= array_muxed5; sdram_dfi_p0_wrdata_en <= array_muxed6; if (sdram_tccdcon_valid) begin sdram_tccdcon_count <= 1'd0; if (1'd1) begin sdram_tccdcon_ready <= 1'd1; end else begin sdram_tccdcon_ready <= 1'd0; end end else begin if ((~sdram_tccdcon_ready)) begin sdram_tccdcon_count <= (sdram_tccdcon_count - 1'd1); if ((sdram_tccdcon_count == 1'd1)) begin sdram_tccdcon_ready <= 1'd1; end end end if (sdram_twtrcon_valid) begin sdram_twtrcon_count <= 3'd4; if (1'd0) begin sdram_twtrcon_ready <= 1'd1; end else begin sdram_twtrcon_ready <= 1'd0; end end else begin if ((~sdram_twtrcon_ready)) begin sdram_twtrcon_count <= (sdram_twtrcon_count - 1'd1); if ((sdram_twtrcon_count == 1'd1)) begin sdram_twtrcon_ready <= 1'd1; end end end subfragments_multiplexer_state <= subfragments_multiplexer_next_state; subfragments_new_master_wdata_ready <= ((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_wdata_ready)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_wdata_ready)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_wdata_ready)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_wdata_ready)); subfragments_new_master_rdata_valid0 <= ((((1'd0 | ((subfragments_roundrobin0_grant == 1'd0) & sdram_interface_bank0_rdata_valid)) | ((subfragments_roundrobin1_grant == 1'd0) & sdram_interface_bank1_rdata_valid)) | ((subfragments_roundrobin2_grant == 1'd0) & sdram_interface_bank2_rdata_valid)) | ((subfragments_roundrobin3_grant == 1'd0) & sdram_interface_bank3_rdata_valid)); subfragments_new_master_rdata_valid1 <= subfragments_new_master_rdata_valid0; subfragments_new_master_rdata_valid2 <= subfragments_new_master_rdata_valid1; subfragments_new_master_rdata_valid3 <= subfragments_new_master_rdata_valid2; if ((litedram_wb_ack | converter_skip)) begin converter_dat_r <= wb_sdram_dat_r; end subfragments_state <= subfragments_next_state; if (converter_counter_subfragments_next_value_ce) begin converter_counter <= converter_counter_subfragments_next_value; end if (converter_reset) begin converter_counter <= 1'd0; subfragments_state <= 1'd0; end if (litedram_wb_ack) begin cmd_consumed <= 1'd0; wdata_consumed <= 1'd0; end else begin if ((port_cmd_valid & port_cmd_ready)) begin cmd_consumed <= 1'd1; end if ((port_wdata_valid & port_wdata_ready)) begin wdata_consumed <= 1'd1; end end uart_phy_sink_ready <= 1'd0; if (((uart_phy_sink_valid & (~uart_phy_tx_busy)) & (~uart_phy_sink_ready))) begin uart_phy_tx_reg <= uart_phy_sink_payload_data; uart_phy_tx_bitcount <= 1'd0; uart_phy_tx_busy <= 1'd1; libresocsim_libresoc_constraintmanager_uart_tx <= 1'd0; end else begin if ((uart_phy_uart_clk_txen & uart_phy_tx_busy)) begin uart_phy_tx_bitcount <= (uart_phy_tx_bitcount + 1'd1); if ((uart_phy_tx_bitcount == 4'd8)) begin libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1; end else begin if ((uart_phy_tx_bitcount == 4'd9)) begin libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1; uart_phy_tx_busy <= 1'd0; uart_phy_sink_ready <= 1'd1; end else begin libresocsim_libresoc_constraintmanager_uart_tx <= uart_phy_tx_reg[0]; uart_phy_tx_reg <= {1'd0, uart_phy_tx_reg[7:1]}; end end end end if (uart_phy_tx_busy) begin {uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= (uart_phy_phase_accumulator_tx + uart_phy_storage); end else begin {uart_phy_uart_clk_txen, uart_phy_phase_accumulator_tx} <= uart_phy_storage; end uart_phy_source_valid <= 1'd0; uart_phy_rx_r <= uart_phy_rx; if ((~uart_phy_rx_busy)) begin if (((~uart_phy_rx) & uart_phy_rx_r)) begin uart_phy_rx_busy <= 1'd1; uart_phy_rx_bitcount <= 1'd0; end end else begin if (uart_phy_uart_clk_rxen) begin uart_phy_rx_bitcount <= (uart_phy_rx_bitcount + 1'd1); if ((uart_phy_rx_bitcount == 1'd0)) begin if (uart_phy_rx) begin uart_phy_rx_busy <= 1'd0; end end else begin if ((uart_phy_rx_bitcount == 4'd9)) begin uart_phy_rx_busy <= 1'd0; if (uart_phy_rx) begin uart_phy_source_payload_data <= uart_phy_rx_reg; uart_phy_source_valid <= 1'd1; end end else begin uart_phy_rx_reg <= {uart_phy_rx, uart_phy_rx_reg[7:1]}; end end end end if (uart_phy_rx_busy) begin {uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= (uart_phy_phase_accumulator_rx + uart_phy_storage); end else begin {uart_phy_uart_clk_rxen, uart_phy_phase_accumulator_rx} <= 32'd2147483648; end if (tx_clear) begin tx_pending <= 1'd0; end tx_old_trigger <= tx_trigger; if (((~tx_trigger) & tx_old_trigger)) begin tx_pending <= 1'd1; end if (rx_clear) begin rx_pending <= 1'd0; end rx_old_trigger <= rx_trigger; if (((~rx_trigger) & rx_old_trigger)) begin rx_pending <= 1'd1; end if (tx_fifo_syncfifo_re) begin tx_fifo_readable <= 1'd1; end else begin if (tx_fifo_re) begin tx_fifo_readable <= 1'd0; end end if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin tx_fifo_produce <= (tx_fifo_produce + 1'd1); end if (tx_fifo_do_read) begin tx_fifo_consume <= (tx_fifo_consume + 1'd1); end if (((tx_fifo_syncfifo_we & tx_fifo_syncfifo_writable) & (~tx_fifo_replace))) begin if ((~tx_fifo_do_read)) begin tx_fifo_level0 <= (tx_fifo_level0 + 1'd1); end end else begin if (tx_fifo_do_read) begin tx_fifo_level0 <= (tx_fifo_level0 - 1'd1); end end if (rx_fifo_syncfifo_re) begin rx_fifo_readable <= 1'd1; end else begin if (rx_fifo_re) begin rx_fifo_readable <= 1'd0; end end if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin rx_fifo_produce <= (rx_fifo_produce + 1'd1); end if (rx_fifo_do_read) begin rx_fifo_consume <= (rx_fifo_consume + 1'd1); end if (((rx_fifo_syncfifo_we & rx_fifo_syncfifo_writable) & (~rx_fifo_replace))) begin if ((~rx_fifo_do_read)) begin rx_fifo_level0 <= (rx_fifo_level0 + 1'd1); end end else begin if (rx_fifo_do_read) begin rx_fifo_level0 <= (rx_fifo_level0 - 1'd1); end end if (reset) begin tx_pending <= 1'd0; tx_old_trigger <= 1'd0; rx_pending <= 1'd0; rx_old_trigger <= 1'd0; tx_fifo_readable <= 1'd0; tx_fifo_level0 <= 5'd0; tx_fifo_produce <= 4'd0; tx_fifo_consume <= 4'd0; rx_fifo_readable <= 1'd0; rx_fifo_level0 <= 5'd0; rx_fifo_produce <= 4'd0; rx_fifo_consume <= 4'd0; end libresocsim_state <= libresocsim_next_state; if (libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0) begin libresocsim_libresocsim_dat_w <= libresocsim_libresocsim_dat_w_libresocsim_next_value0; end if (libresocsim_libresocsim_adr_libresocsim_next_value_ce1) begin libresocsim_libresocsim_adr <= libresocsim_libresocsim_adr_libresocsim_next_value1; end if (libresocsim_libresocsim_we_libresocsim_next_value_ce2) begin libresocsim_libresocsim_we <= libresocsim_libresocsim_we_libresocsim_next_value2; end case (libresocsim_grant) 1'd0: begin if ((~libresocsim_request[0])) begin if (libresocsim_request[1]) begin libresocsim_grant <= 1'd1; end else begin if (libresocsim_request[2]) begin libresocsim_grant <= 2'd2; end end end end 1'd1: begin if ((~libresocsim_request[1])) begin if (libresocsim_request[2]) begin libresocsim_grant <= 2'd2; end else begin if (libresocsim_request[0]) begin libresocsim_grant <= 1'd0; end end end end 2'd2: begin if ((~libresocsim_request[2])) begin if (libresocsim_request[0]) begin libresocsim_grant <= 1'd0; end else begin if (libresocsim_request[1]) begin libresocsim_grant <= 1'd1; end end end end endcase libresocsim_slave_sel_r <= libresocsim_slave_sel; if (libresocsim_wait) begin if ((~libresocsim_done)) begin libresocsim_count <= (libresocsim_count - 1'd1); end end else begin libresocsim_count <= 20'd1000000; end libresocsim_interface0_bank_bus_dat_r <= 1'd0; if (libresocsim_csrbank0_sel) begin case (libresocsim_interface0_bank_bus_adr[3:0]) 1'd0: begin libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_reset0_w; end 1'd1: begin libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch3_w; end 2'd2: begin libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch2_w; end 2'd3: begin libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch1_w; end 3'd4: begin libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_scratch0_w; end 3'd5: begin libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors3_w; end 3'd6: begin libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors2_w; end 3'd7: begin libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors1_w; end 4'd8: begin libresocsim_interface0_bank_bus_dat_r <= libresocsim_csrbank0_bus_errors0_w; end endcase end if (libresocsim_csrbank0_reset0_re) begin libresocsim_reset_storage <= libresocsim_csrbank0_reset0_r; end libresocsim_reset_re <= libresocsim_csrbank0_reset0_re; if (libresocsim_csrbank0_scratch3_re) begin libresocsim_scratch_storage[31:24] <= libresocsim_csrbank0_scratch3_r; end if (libresocsim_csrbank0_scratch2_re) begin libresocsim_scratch_storage[23:16] <= libresocsim_csrbank0_scratch2_r; end if (libresocsim_csrbank0_scratch1_re) begin libresocsim_scratch_storage[15:8] <= libresocsim_csrbank0_scratch1_r; end if (libresocsim_csrbank0_scratch0_re) begin libresocsim_scratch_storage[7:0] <= libresocsim_csrbank0_scratch0_r; end libresocsim_scratch_re <= libresocsim_csrbank0_scratch0_re; libresocsim_interface1_bank_bus_dat_r <= 1'd0; if (libresocsim_csrbank1_sel) begin case (libresocsim_interface1_bank_bus_adr[1:0]) 1'd0: begin libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_oe0_w; end 1'd1: begin libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_in_w; end 2'd2: begin libresocsim_interface1_bank_bus_dat_r <= libresocsim_csrbank1_out0_w; end endcase end if (libresocsim_csrbank1_oe0_re) begin gpio0_oe_storage[7:0] <= libresocsim_csrbank1_oe0_r; end gpio0_oe_re <= libresocsim_csrbank1_oe0_re; if (libresocsim_csrbank1_out0_re) begin gpio0_out_storage[7:0] <= libresocsim_csrbank1_out0_r; end gpio0_out_re <= libresocsim_csrbank1_out0_re; libresocsim_interface2_bank_bus_dat_r <= 1'd0; if (libresocsim_csrbank2_sel) begin case (libresocsim_interface2_bank_bus_adr[1:0]) 1'd0: begin libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_oe0_w; end 1'd1: begin libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_in_w; end 2'd2: begin libresocsim_interface2_bank_bus_dat_r <= libresocsim_csrbank2_out0_w; end endcase end if (libresocsim_csrbank2_oe0_re) begin gpio1_oe_storage[7:0] <= libresocsim_csrbank2_oe0_r; end gpio1_oe_re <= libresocsim_csrbank2_oe0_re; if (libresocsim_csrbank2_out0_re) begin gpio1_out_storage[7:0] <= libresocsim_csrbank2_out0_r; end gpio1_out_re <= libresocsim_csrbank2_out0_re; libresocsim_interface3_bank_bus_dat_r <= 1'd0; if (libresocsim_csrbank3_sel) begin case (libresocsim_interface3_bank_bus_adr[0]) 1'd0: begin libresocsim_interface3_bank_bus_dat_r <= libresocsim_csrbank3_w0_w; end 1'd1: begin libresocsim_interface3_bank_bus_dat_r <= libresocsim_csrbank3_r_w; end endcase end if (libresocsim_csrbank3_w0_re) begin i2c_storage[2:0] <= libresocsim_csrbank3_w0_r; end i2c_re <= libresocsim_csrbank3_w0_re; libresocsim_interface4_bank_bus_dat_r <= 1'd0; if (libresocsim_csrbank4_sel) begin case (libresocsim_interface4_bank_bus_adr[3:0]) 1'd0: begin libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_control0_w; end 1'd1: begin libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_command0_w; end 2'd2: begin libresocsim_interface4_bank_bus_dat_r <= sdram_command_issue_w; end 2'd3: begin libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_address1_w; end 3'd4: begin libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_address0_w; end 3'd5: begin libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_baddress0_w; end 3'd6: begin libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_wrdata1_w; end 3'd7: begin libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_wrdata0_w; end 4'd8: begin libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_rddata1_w; end 4'd9: begin libresocsim_interface4_bank_bus_dat_r <= libresocsim_csrbank4_dfii_pi0_rddata0_w; end endcase end if (libresocsim_csrbank4_dfii_control0_re) begin sdram_storage[3:0] <= libresocsim_csrbank4_dfii_control0_r; end sdram_re <= libresocsim_csrbank4_dfii_control0_re; if (libresocsim_csrbank4_dfii_pi0_command0_re) begin sdram_command_storage[5:0] <= libresocsim_csrbank4_dfii_pi0_command0_r; end sdram_command_re <= libresocsim_csrbank4_dfii_pi0_command0_re; if (libresocsim_csrbank4_dfii_pi0_address1_re) begin sdram_address_storage[12:8] <= libresocsim_csrbank4_dfii_pi0_address1_r; end if (libresocsim_csrbank4_dfii_pi0_address0_re) begin sdram_address_storage[7:0] <= libresocsim_csrbank4_dfii_pi0_address0_r; end sdram_address_re <= libresocsim_csrbank4_dfii_pi0_address0_re; if (libresocsim_csrbank4_dfii_pi0_baddress0_re) begin sdram_baddress_storage[1:0] <= libresocsim_csrbank4_dfii_pi0_baddress0_r; end sdram_baddress_re <= libresocsim_csrbank4_dfii_pi0_baddress0_re; if (libresocsim_csrbank4_dfii_pi0_wrdata1_re) begin sdram_wrdata_storage[15:8] <= libresocsim_csrbank4_dfii_pi0_wrdata1_r; end if (libresocsim_csrbank4_dfii_pi0_wrdata0_re) begin sdram_wrdata_storage[7:0] <= libresocsim_csrbank4_dfii_pi0_wrdata0_r; end sdram_wrdata_re <= libresocsim_csrbank4_dfii_pi0_wrdata0_re; libresocsim_interface5_bank_bus_dat_r <= 1'd0; if (libresocsim_csrbank5_sel) begin case (libresocsim_interface5_bank_bus_adr[4:0]) 1'd0: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load3_w; end 1'd1: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load2_w; end 2'd2: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load1_w; end 2'd3: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_load0_w; end 3'd4: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload3_w; end 3'd5: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload2_w; end 3'd6: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload1_w; end 3'd7: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_reload0_w; end 4'd8: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_en0_w; end 4'd9: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_update_value0_w; end 4'd10: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value3_w; end 4'd11: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value2_w; end 4'd12: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value1_w; end 4'd13: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_value0_w; end 4'd14: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_eventmanager_status_w; end 4'd15: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_eventmanager_pending_w; end 5'd16: begin libresocsim_interface5_bank_bus_dat_r <= libresocsim_csrbank5_ev_enable0_w; end endcase end if (libresocsim_csrbank5_load3_re) begin libresocsim_load_storage[31:24] <= libresocsim_csrbank5_load3_r; end if (libresocsim_csrbank5_load2_re) begin libresocsim_load_storage[23:16] <= libresocsim_csrbank5_load2_r; end if (libresocsim_csrbank5_load1_re) begin libresocsim_load_storage[15:8] <= libresocsim_csrbank5_load1_r; end if (libresocsim_csrbank5_load0_re) begin libresocsim_load_storage[7:0] <= libresocsim_csrbank5_load0_r; end libresocsim_load_re <= libresocsim_csrbank5_load0_re; if (libresocsim_csrbank5_reload3_re) begin libresocsim_reload_storage[31:24] <= libresocsim_csrbank5_reload3_r; end if (libresocsim_csrbank5_reload2_re) begin libresocsim_reload_storage[23:16] <= libresocsim_csrbank5_reload2_r; end if (libresocsim_csrbank5_reload1_re) begin libresocsim_reload_storage[15:8] <= libresocsim_csrbank5_reload1_r; end if (libresocsim_csrbank5_reload0_re) begin libresocsim_reload_storage[7:0] <= libresocsim_csrbank5_reload0_r; end libresocsim_reload_re <= libresocsim_csrbank5_reload0_re; if (libresocsim_csrbank5_en0_re) begin libresocsim_en_storage <= libresocsim_csrbank5_en0_r; end libresocsim_en_re <= libresocsim_csrbank5_en0_re; if (libresocsim_csrbank5_update_value0_re) begin libresocsim_update_value_storage <= libresocsim_csrbank5_update_value0_r; end libresocsim_update_value_re <= libresocsim_csrbank5_update_value0_re; if (libresocsim_csrbank5_ev_enable0_re) begin libresocsim_eventmanager_storage <= libresocsim_csrbank5_ev_enable0_r; end libresocsim_eventmanager_re <= libresocsim_csrbank5_ev_enable0_re; libresocsim_interface6_bank_bus_dat_r <= 1'd0; if (libresocsim_csrbank6_sel) begin case (libresocsim_interface6_bank_bus_adr[2:0]) 1'd0: begin libresocsim_interface6_bank_bus_dat_r <= rxtx_w; end 1'd1: begin libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_txfull_w; end 2'd2: begin libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_rxempty_w; end 2'd3: begin libresocsim_interface6_bank_bus_dat_r <= eventmanager_status_w; end 3'd4: begin libresocsim_interface6_bank_bus_dat_r <= eventmanager_pending_w; end 3'd5: begin libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_ev_enable0_w; end 3'd6: begin libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_txempty_w; end 3'd7: begin libresocsim_interface6_bank_bus_dat_r <= libresocsim_csrbank6_rxfull_w; end endcase end if (libresocsim_csrbank6_ev_enable0_re) begin eventmanager_storage[1:0] <= libresocsim_csrbank6_ev_enable0_r; end eventmanager_re <= libresocsim_csrbank6_ev_enable0_re; libresocsim_interface7_bank_bus_dat_r <= 1'd0; if (libresocsim_csrbank7_sel) begin case (libresocsim_interface7_bank_bus_adr[1:0]) 1'd0: begin libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word3_w; end 1'd1: begin libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word2_w; end 2'd2: begin libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word1_w; end 2'd3: begin libresocsim_interface7_bank_bus_dat_r <= libresocsim_csrbank7_tuning_word0_w; end endcase end if (libresocsim_csrbank7_tuning_word3_re) begin uart_phy_storage[31:24] <= libresocsim_csrbank7_tuning_word3_r; end if (libresocsim_csrbank7_tuning_word2_re) begin uart_phy_storage[23:16] <= libresocsim_csrbank7_tuning_word2_r; end if (libresocsim_csrbank7_tuning_word1_re) begin uart_phy_storage[15:8] <= libresocsim_csrbank7_tuning_word1_r; end if (libresocsim_csrbank7_tuning_word0_re) begin uart_phy_storage[7:0] <= libresocsim_csrbank7_tuning_word0_r; end uart_phy_re <= libresocsim_csrbank7_tuning_word0_re; if (sys_rst_1) begin libresocsim_reset_storage <= 1'd0; libresocsim_reset_re <= 1'd0; libresocsim_scratch_storage <= 32'd305419896; libresocsim_scratch_re <= 1'd0; libresocsim_bus_errors <= 32'd0; libresocsim_libresoc_constraintmanager_uart_tx <= 1'd1; libresocsim_converter0_counter <= 1'd0; libresocsim_converter1_counter <= 1'd0; libresocsim_ram_bus_ack <= 1'd0; libresocsim_load_storage <= 32'd0; libresocsim_load_re <= 1'd0; libresocsim_reload_storage <= 32'd0; libresocsim_reload_re <= 1'd0; libresocsim_en_storage <= 1'd0; libresocsim_en_re <= 1'd0; libresocsim_update_value_storage <= 1'd0; libresocsim_update_value_re <= 1'd0; libresocsim_value_status <= 32'd0; libresocsim_zero_pending <= 1'd0; libresocsim_zero_old_trigger <= 1'd0; libresocsim_eventmanager_storage <= 1'd0; libresocsim_eventmanager_re <= 1'd0; libresocsim_value <= 32'd0; ram_bus_ram_bus_ack <= 1'd0; dfi_p0_rddata_valid <= 1'd0; rddata_en <= 3'd0; sdram_storage <= 4'd1; sdram_re <= 1'd0; sdram_command_storage <= 6'd0; sdram_command_re <= 1'd0; sdram_address_re <= 1'd0; sdram_baddress_re <= 1'd0; sdram_wrdata_re <= 1'd0; sdram_status <= 16'd0; sdram_dfi_p0_address <= 13'd0; sdram_dfi_p0_bank <= 2'd0; sdram_dfi_p0_cas_n <= 1'd1; sdram_dfi_p0_cs_n <= 1'd1; sdram_dfi_p0_ras_n <= 1'd1; sdram_dfi_p0_we_n <= 1'd1; sdram_dfi_p0_wrdata_en <= 1'd0; sdram_dfi_p0_rddata_en <= 1'd0; sdram_timer_count1 <= 10'd781; sdram_postponer_req_o <= 1'd0; sdram_postponer_count <= 1'd0; sdram_sequencer_done1 <= 1'd0; sdram_sequencer_counter <= 4'd0; sdram_sequencer_count <= 1'd0; sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine0_row <= 13'd0; sdram_bankmachine0_row_opened <= 1'd0; sdram_bankmachine0_twtpcon_ready <= 1'd0; sdram_bankmachine0_twtpcon_count <= 3'd0; sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine1_row <= 13'd0; sdram_bankmachine1_row_opened <= 1'd0; sdram_bankmachine1_twtpcon_ready <= 1'd0; sdram_bankmachine1_twtpcon_count <= 3'd0; sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine2_row <= 13'd0; sdram_bankmachine2_row_opened <= 1'd0; sdram_bankmachine2_twtpcon_ready <= 1'd0; sdram_bankmachine2_twtpcon_count <= 3'd0; sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0; sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0; sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0; sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0; sdram_bankmachine3_row <= 13'd0; sdram_bankmachine3_row_opened <= 1'd0; sdram_bankmachine3_twtpcon_ready <= 1'd0; sdram_bankmachine3_twtpcon_count <= 3'd0; sdram_choose_cmd_grant <= 2'd0; sdram_choose_req_grant <= 2'd0; sdram_tccdcon_ready <= 1'd0; sdram_tccdcon_count <= 1'd0; sdram_twtrcon_ready <= 1'd0; sdram_twtrcon_count <= 3'd0; sdram_time0 <= 5'd0; sdram_time1 <= 4'd0; converter_counter <= 1'd0; cmd_consumed <= 1'd0; wdata_consumed <= 1'd0; uart_phy_storage <= 32'd9895604; uart_phy_re <= 1'd0; uart_phy_sink_ready <= 1'd0; uart_phy_uart_clk_txen <= 1'd0; uart_phy_tx_busy <= 1'd0; uart_phy_source_valid <= 1'd0; uart_phy_uart_clk_rxen <= 1'd0; uart_phy_rx_r <= 1'd0; uart_phy_rx_busy <= 1'd0; tx_pending <= 1'd0; tx_old_trigger <= 1'd0; rx_pending <= 1'd0; rx_old_trigger <= 1'd0; eventmanager_storage <= 2'd0; eventmanager_re <= 1'd0; tx_fifo_readable <= 1'd0; tx_fifo_level0 <= 5'd0; tx_fifo_produce <= 4'd0; tx_fifo_consume <= 4'd0; rx_fifo_readable <= 1'd0; rx_fifo_level0 <= 5'd0; rx_fifo_produce <= 4'd0; rx_fifo_consume <= 4'd0; gpio0_oe_storage <= 8'd0; gpio0_oe_re <= 1'd0; gpio0_out_storage <= 8'd0; gpio0_out_re <= 1'd0; gpio1_oe_storage <= 8'd0; gpio1_oe_re <= 1'd0; gpio1_out_storage <= 8'd0; gpio1_out_re <= 1'd0; dummy <= 40'd0; i2c_storage <= 3'd0; i2c_re <= 1'd0; subfragments_converter0_state <= 1'd0; subfragments_converter1_state <= 1'd0; subfragments_refresher_state <= 2'd0; subfragments_bankmachine0_state <= 3'd0; subfragments_bankmachine1_state <= 3'd0; subfragments_bankmachine2_state <= 3'd0; subfragments_bankmachine3_state <= 3'd0; subfragments_multiplexer_state <= 3'd0; subfragments_new_master_wdata_ready <= 1'd0; subfragments_new_master_rdata_valid0 <= 1'd0; subfragments_new_master_rdata_valid1 <= 1'd0; subfragments_new_master_rdata_valid2 <= 1'd0; subfragments_new_master_rdata_valid3 <= 1'd0; subfragments_state <= 1'd0; libresocsim_libresocsim_we <= 1'd0; libresocsim_grant <= 2'd0; libresocsim_slave_sel_r <= 6'd0; libresocsim_count <= 20'd1000000; libresocsim_state <= 2'd0; end regs0 <= libresocsim_libresoc_constraintmanager_uart_rx; regs1 <= regs0; end reg [31:0] mem[0:127]; reg [6:0] memadr; always @(posedge sys_clk_1) begin if (libresocsim_we[0]) mem[libresocsim_adr][7:0] <= libresocsim_dat_w[7:0]; if (libresocsim_we[1]) mem[libresocsim_adr][15:8] <= libresocsim_dat_w[15:8]; if (libresocsim_we[2]) mem[libresocsim_adr][23:16] <= libresocsim_dat_w[23:16]; if (libresocsim_we[3]) mem[libresocsim_adr][31:24] <= libresocsim_dat_w[31:24]; memadr <= libresocsim_adr; end assign libresocsim_dat_r = mem[memadr]; initial begin $readmemh("mem.init", mem); end reg [31:0] mem_1[0:31]; reg [4:0] memadr_1; always @(posedge sys_clk_1) begin if (ram_we[0]) mem_1[ram_adr][7:0] <= ram_dat_w[7:0]; if (ram_we[1]) mem_1[ram_adr][15:8] <= ram_dat_w[15:8]; if (ram_we[2]) mem_1[ram_adr][23:16] <= ram_dat_w[23:16]; if (ram_we[3]) mem_1[ram_adr][31:24] <= ram_dat_w[31:24]; memadr_1 <= ram_adr; end assign ram_dat_r = mem_1[memadr_1]; initial begin $readmemh("mem_1.init", mem_1); end reg [24:0] storage[0:7]; reg [24:0] memdat; always @(posedge sys_clk_1) begin if (sdram_bankmachine0_cmd_buffer_lookahead_wrport_we) storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; memdat <= storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk_1) begin end assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat; assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_1[0:7]; reg [24:0] memdat_1; always @(posedge sys_clk_1) begin if (sdram_bankmachine1_cmd_buffer_lookahead_wrport_we) storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; memdat_1 <= storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk_1) begin end assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1; assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_2[0:7]; reg [24:0] memdat_2; always @(posedge sys_clk_1) begin if (sdram_bankmachine2_cmd_buffer_lookahead_wrport_we) storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; memdat_2 <= storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk_1) begin end assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2; assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr]; reg [24:0] storage_3[0:7]; reg [24:0] memdat_3; always @(posedge sys_clk_1) begin if (sdram_bankmachine3_cmd_buffer_lookahead_wrport_we) storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; memdat_3 <= storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr]; end always @(posedge sys_clk_1) begin end assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3; assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr]; reg [9:0] storage_4[0:15]; reg [9:0] memdat_4; reg [9:0] memdat_5; always @(posedge sys_clk_1) begin if (tx_fifo_wrport_we) storage_4[tx_fifo_wrport_adr] <= tx_fifo_wrport_dat_w; memdat_4 <= storage_4[tx_fifo_wrport_adr]; end always @(posedge sys_clk_1) begin if (tx_fifo_rdport_re) memdat_5 <= storage_4[tx_fifo_rdport_adr]; end assign tx_fifo_wrport_dat_r = memdat_4; assign tx_fifo_rdport_dat_r = memdat_5; reg [9:0] storage_5[0:15]; reg [9:0] memdat_6; reg [9:0] memdat_7; always @(posedge sys_clk_1) begin if (rx_fifo_wrport_we) storage_5[rx_fifo_wrport_adr] <= rx_fifo_wrport_dat_w; memdat_6 <= storage_5[rx_fifo_wrport_adr]; end always @(posedge sys_clk_1) begin if (rx_fifo_rdport_re) memdat_7 <= storage_5[rx_fifo_rdport_adr]; end assign rx_fifo_wrport_dat_r = memdat_6; assign rx_fifo_rdport_dat_r = memdat_7; test_issuer test_issuer( .TAP_bus__tck(libresocsim_libresoc_jtag_tck), .TAP_bus__tdi(libresocsim_libresoc_jtag_tdi), .TAP_bus__tms(libresocsim_libresoc_jtag_tms), .clk(sys_clk_1), .core_bigendian_i(1'd0), .dbus__ack(libresocsim_libresoc_dbus_ack), .dbus__bte(1'd0), .dbus__cti(1'd0), .dbus__dat_r(libresocsim_libresoc_dbus_dat_r), .dbus__err(libresocsim_libresoc_dbus_err), .eint_0__pad__i(eint_0), .eint_1__pad__i(eint_1), .eint_2__pad__i(eint_2), .gpio_e10__core__o(libresocsim_libresoc_constraintmanager_gpio_o[10]), .gpio_e10__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[10]), .gpio_e10__pad__i(gpio_i[10]), .gpio_e11__core__o(libresocsim_libresoc_constraintmanager_gpio_o[11]), .gpio_e11__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[11]), .gpio_e11__pad__i(gpio_i[11]), .gpio_e12__core__o(libresocsim_libresoc_constraintmanager_gpio_o[12]), .gpio_e12__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[12]), .gpio_e12__pad__i(gpio_i[12]), .gpio_e13__core__o(libresocsim_libresoc_constraintmanager_gpio_o[13]), .gpio_e13__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[13]), .gpio_e13__pad__i(gpio_i[13]), .gpio_e14__core__o(libresocsim_libresoc_constraintmanager_gpio_o[14]), .gpio_e14__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[14]), .gpio_e14__pad__i(gpio_i[14]), .gpio_e15__core__o(libresocsim_libresoc_constraintmanager_gpio_o[15]), .gpio_e15__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[15]), .gpio_e15__pad__i(gpio_i[15]), .gpio_e8__core__o(libresocsim_libresoc_constraintmanager_gpio_o[8]), .gpio_e8__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[8]), .gpio_e8__pad__i(gpio_i[8]), .gpio_e9__core__o(libresocsim_libresoc_constraintmanager_gpio_o[9]), .gpio_e9__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[9]), .gpio_e9__pad__i(gpio_i[9]), .gpio_s0__core__o(libresocsim_libresoc_constraintmanager_gpio_o[0]), .gpio_s0__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[0]), .gpio_s0__pad__i(gpio_i[0]), .gpio_s1__core__o(libresocsim_libresoc_constraintmanager_gpio_o[1]), .gpio_s1__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[1]), .gpio_s1__pad__i(gpio_i[1]), .gpio_s2__core__o(libresocsim_libresoc_constraintmanager_gpio_o[2]), .gpio_s2__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[2]), .gpio_s2__pad__i(gpio_i[2]), .gpio_s3__core__o(libresocsim_libresoc_constraintmanager_gpio_o[3]), .gpio_s3__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[3]), .gpio_s3__pad__i(gpio_i[3]), .gpio_s4__core__o(libresocsim_libresoc_constraintmanager_gpio_o[4]), .gpio_s4__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[4]), .gpio_s4__pad__i(gpio_i[4]), .gpio_s5__core__o(libresocsim_libresoc_constraintmanager_gpio_o[5]), .gpio_s5__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[5]), .gpio_s5__pad__i(gpio_i[5]), .gpio_s6__core__o(libresocsim_libresoc_constraintmanager_gpio_o[6]), .gpio_s6__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[6]), .gpio_s6__pad__i(gpio_i[6]), .gpio_s7__core__o(libresocsim_libresoc_constraintmanager_gpio_o[7]), .gpio_s7__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[7]), .gpio_s7__pad__i(gpio_i[7]), .ibus__ack(libresocsim_libresoc_ibus_ack), .ibus__bte(1'd0), .ibus__cti(1'd0), .ibus__dat_r(libresocsim_libresoc_ibus_dat_r), .ibus__err(libresocsim_libresoc_ibus_err), .icp_wb__adr(libresocsim_libresoc_xics_icp_adr), .icp_wb__cyc(libresocsim_libresoc_xics_icp_cyc), .icp_wb__dat_w(libresocsim_libresoc_xics_icp_dat_w), .icp_wb__sel(libresocsim_libresoc_xics_icp_sel), .icp_wb__stb(libresocsim_libresoc_xics_icp_stb), .icp_wb__we(libresocsim_libresoc_xics_icp_we), .ics_wb__adr(libresocsim_libresoc_xics_ics_adr), .ics_wb__cyc(libresocsim_libresoc_xics_ics_cyc), .ics_wb__dat_w(libresocsim_libresoc_xics_ics_dat_w), .ics_wb__sel(libresocsim_libresoc_xics_ics_sel), .ics_wb__stb(libresocsim_libresoc_xics_ics_stb), .ics_wb__we(libresocsim_libresoc_xics_ics_we), .int_level_i(libresocsim_libresoc_interrupt), .jtag_wb__ack(libresocsim_libresoc_jtag_wb_ack), .jtag_wb__dat_r(libresocsim_libresoc_jtag_wb_dat_r), .jtag_wb__err(libresocsim_libresoc_jtag_wb_err), .mspi0_clk__core__o(libresocsim_libresoc_constraintmanager_spimaster_clk), .mspi0_cs_n__core__o(libresocsim_libresoc_constraintmanager_spimaster_cs_n), .mspi0_miso__pad__i(spimaster_miso), .mspi0_mosi__core__o(libresocsim_libresoc_constraintmanager_spimaster_mosi), .mtwi_scl__core__o(libresocsim_libresoc_constraintmanager_i2c_scl), .mtwi_sda__core__o(libresocsim_libresoc_constraintmanager_i2c_sda_o), .mtwi_sda__core__oe(libresocsim_libresoc_constraintmanager_i2c_sda_oe), .mtwi_sda__pad__i(i2c_sda_i), .pc_i(libresocsim_libresoc0), .pc_i_ok(1'd0), .rst((sys_rst_1 | libresocsim_libresoc_reset)), .sdr_a_0__core__o(libresocsim_libresoc_constraintmanager_sdram_a[0]), .sdr_a_10__core__o(libresocsim_libresoc_constraintmanager_sdram_a[10]), .sdr_a_11__core__o(libresocsim_libresoc_constraintmanager_sdram_a[11]), .sdr_a_12__core__o(libresocsim_libresoc_constraintmanager_sdram_a[12]), .sdr_a_1__core__o(libresocsim_libresoc_constraintmanager_sdram_a[1]), .sdr_a_2__core__o(libresocsim_libresoc_constraintmanager_sdram_a[2]), .sdr_a_3__core__o(libresocsim_libresoc_constraintmanager_sdram_a[3]), .sdr_a_4__core__o(libresocsim_libresoc_constraintmanager_sdram_a[4]), .sdr_a_5__core__o(libresocsim_libresoc_constraintmanager_sdram_a[5]), .sdr_a_6__core__o(libresocsim_libresoc_constraintmanager_sdram_a[6]), .sdr_a_7__core__o(libresocsim_libresoc_constraintmanager_sdram_a[7]), .sdr_a_8__core__o(libresocsim_libresoc_constraintmanager_sdram_a[8]), .sdr_a_9__core__o(libresocsim_libresoc_constraintmanager_sdram_a[9]), .sdr_ba_0__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[0]), .sdr_ba_1__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[1]), .sdr_cas_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cas_n), .sdr_cke__core__o(libresocsim_libresoc_constraintmanager_sdram_cke), .sdr_clock__core__o(libresocsim_libresoc_constraintmanager_sdram_clock), .sdr_cs_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cs_n), .sdr_dm_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[0]), .sdr_dm_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[1]), .sdr_dq_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[0]), .sdr_dq_0__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[0]), .sdr_dq_0__pad__i(sdram_dq_i[0]), .sdr_dq_10__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[10]), .sdr_dq_10__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[10]), .sdr_dq_10__pad__i(sdram_dq_i[10]), .sdr_dq_11__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[11]), .sdr_dq_11__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[11]), .sdr_dq_11__pad__i(sdram_dq_i[11]), .sdr_dq_12__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[12]), .sdr_dq_12__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[12]), .sdr_dq_12__pad__i(sdram_dq_i[12]), .sdr_dq_13__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[13]), .sdr_dq_13__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[13]), .sdr_dq_13__pad__i(sdram_dq_i[13]), .sdr_dq_14__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[14]), .sdr_dq_14__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[14]), .sdr_dq_14__pad__i(sdram_dq_i[14]), .sdr_dq_15__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[15]), .sdr_dq_15__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[15]), .sdr_dq_15__pad__i(sdram_dq_i[15]), .sdr_dq_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[1]), .sdr_dq_1__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[1]), .sdr_dq_1__pad__i(sdram_dq_i[1]), .sdr_dq_2__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[2]), .sdr_dq_2__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[2]), .sdr_dq_2__pad__i(sdram_dq_i[2]), .sdr_dq_3__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[3]), .sdr_dq_3__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[3]), .sdr_dq_3__pad__i(sdram_dq_i[3]), .sdr_dq_4__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[4]), .sdr_dq_4__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[4]), .sdr_dq_4__pad__i(sdram_dq_i[4]), .sdr_dq_5__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[5]), .sdr_dq_5__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[5]), .sdr_dq_5__pad__i(sdram_dq_i[5]), .sdr_dq_6__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[6]), .sdr_dq_6__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[6]), .sdr_dq_6__pad__i(sdram_dq_i[6]), .sdr_dq_7__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[7]), .sdr_dq_7__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[7]), .sdr_dq_7__pad__i(sdram_dq_i[7]), .sdr_dq_8__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[8]), .sdr_dq_8__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[8]), .sdr_dq_8__pad__i(sdram_dq_i[8]), .sdr_dq_9__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[9]), .sdr_dq_9__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[9]), .sdr_dq_9__pad__i(sdram_dq_i[9]), .sdr_ras_n__core__o(libresocsim_libresoc_constraintmanager_sdram_ras_n), .sdr_we_n__core__o(libresocsim_libresoc_constraintmanager_sdram_we_n), .TAP_bus__tdo(libresocsim_libresoc_jtag_tdo), .busy_o(libresocsim_libresoc1), .dbus__adr(libresocsim_libresoc_dbus_adr), .dbus__cyc(libresocsim_libresoc_dbus_cyc), .dbus__dat_w(libresocsim_libresoc_dbus_dat_w), .dbus__sel(libresocsim_libresoc_dbus_sel), .dbus__stb(libresocsim_libresoc_dbus_stb), .dbus__we(libresocsim_libresoc_dbus_we), .eint_0__core__i(libresocsim_libresoc_constraintmanager_eint_0), .eint_1__core__i(libresocsim_libresoc_constraintmanager_eint_1), .eint_2__core__i(libresocsim_libresoc_constraintmanager_eint_2), .gpio_e10__core__i(libresocsim_libresoc_constraintmanager_gpio_i[10]), .gpio_e10__pad__o(gpio_o[10]), .gpio_e10__pad__oe(gpio_oe[10]), .gpio_e11__core__i(libresocsim_libresoc_constraintmanager_gpio_i[11]), .gpio_e11__pad__o(gpio_o[11]), .gpio_e11__pad__oe(gpio_oe[11]), .gpio_e12__core__i(libresocsim_libresoc_constraintmanager_gpio_i[12]), .gpio_e12__pad__o(gpio_o[12]), .gpio_e12__pad__oe(gpio_oe[12]), .gpio_e13__core__i(libresocsim_libresoc_constraintmanager_gpio_i[13]), .gpio_e13__pad__o(gpio_o[13]), .gpio_e13__pad__oe(gpio_oe[13]), .gpio_e14__core__i(libresocsim_libresoc_constraintmanager_gpio_i[14]), .gpio_e14__pad__o(gpio_o[14]), .gpio_e14__pad__oe(gpio_oe[14]), .gpio_e15__core__i(libresocsim_libresoc_constraintmanager_gpio_i[15]), .gpio_e15__pad__o(gpio_o[15]), .gpio_e15__pad__oe(gpio_oe[15]), .gpio_e8__core__i(libresocsim_libresoc_constraintmanager_gpio_i[8]), .gpio_e8__pad__o(gpio_o[8]), .gpio_e8__pad__oe(gpio_oe[8]), .gpio_e9__core__i(libresocsim_libresoc_constraintmanager_gpio_i[9]), .gpio_e9__pad__o(gpio_o[9]), .gpio_e9__pad__oe(gpio_oe[9]), .gpio_s0__core__i(libresocsim_libresoc_constraintmanager_gpio_i[0]), .gpio_s0__pad__o(gpio_o[0]), .gpio_s0__pad__oe(gpio_oe[0]), .gpio_s1__core__i(libresocsim_libresoc_constraintmanager_gpio_i[1]), .gpio_s1__pad__o(gpio_o[1]), .gpio_s1__pad__oe(gpio_oe[1]), .gpio_s2__core__i(libresocsim_libresoc_constraintmanager_gpio_i[2]), .gpio_s2__pad__o(gpio_o[2]), .gpio_s2__pad__oe(gpio_oe[2]), .gpio_s3__core__i(libresocsim_libresoc_constraintmanager_gpio_i[3]), .gpio_s3__pad__o(gpio_o[3]), .gpio_s3__pad__oe(gpio_oe[3]), .gpio_s4__core__i(libresocsim_libresoc_constraintmanager_gpio_i[4]), .gpio_s4__pad__o(gpio_o[4]), .gpio_s4__pad__oe(gpio_oe[4]), .gpio_s5__core__i(libresocsim_libresoc_constraintmanager_gpio_i[5]), .gpio_s5__pad__o(gpio_o[5]), .gpio_s5__pad__oe(gpio_oe[5]), .gpio_s6__core__i(libresocsim_libresoc_constraintmanager_gpio_i[6]), .gpio_s6__pad__o(gpio_o[6]), .gpio_s6__pad__oe(gpio_oe[6]), .gpio_s7__core__i(libresocsim_libresoc_constraintmanager_gpio_i[7]), .gpio_s7__pad__o(gpio_o[7]), .gpio_s7__pad__oe(gpio_oe[7]), .ibus__adr(libresocsim_libresoc_ibus_adr), .ibus__cyc(libresocsim_libresoc_ibus_cyc), .ibus__dat_w(libresocsim_libresoc_ibus_dat_w), .ibus__sel(libresocsim_libresoc_ibus_sel), .ibus__stb(libresocsim_libresoc_ibus_stb), .ibus__we(libresocsim_libresoc_ibus_we), .icp_wb__ack(libresocsim_libresoc_xics_icp_ack), .icp_wb__dat_r(libresocsim_libresoc_xics_icp_dat_r), .icp_wb__err(libresocsim_libresoc_xics_icp_err), .ics_wb__ack(libresocsim_libresoc_xics_ics_ack), .ics_wb__dat_r(libresocsim_libresoc_xics_ics_dat_r), .ics_wb__err(libresocsim_libresoc_xics_ics_err), .jtag_wb__adr(libresocsim_libresoc_jtag_wb_adr), .jtag_wb__cyc(libresocsim_libresoc_jtag_wb_cyc), .jtag_wb__dat_w(libresocsim_libresoc_jtag_wb_dat_w), .jtag_wb__sel(libresocsim_libresoc_jtag_wb_sel), .jtag_wb__stb(libresocsim_libresoc_jtag_wb_stb), .jtag_wb__we(libresocsim_libresoc_jtag_wb_we), .memerr_o(libresocsim_libresoc2), .mspi0_clk__pad__o(spimaster_clk), .mspi0_cs_n__pad__o(spimaster_cs_n), .mspi0_miso__core__i(libresocsim_libresoc_constraintmanager_spimaster_miso), .mspi0_mosi__pad__o(spimaster_mosi), .mtwi_scl__pad__o(i2c_scl), .mtwi_sda__core__i(libresocsim_libresoc_constraintmanager_i2c_sda_i), .mtwi_sda__pad__o(i2c_sda_o), .mtwi_sda__pad__oe(i2c_sda_oe), .pc_o(libresocsim_libresoc3), .sdr_a_0__pad__o(sdram_a[0]), .sdr_a_10__pad__o(sdram_a[10]), .sdr_a_11__pad__o(sdram_a[11]), .sdr_a_12__pad__o(sdram_a[12]), .sdr_a_1__pad__o(sdram_a[1]), .sdr_a_2__pad__o(sdram_a[2]), .sdr_a_3__pad__o(sdram_a[3]), .sdr_a_4__pad__o(sdram_a[4]), .sdr_a_5__pad__o(sdram_a[5]), .sdr_a_6__pad__o(sdram_a[6]), .sdr_a_7__pad__o(sdram_a[7]), .sdr_a_8__pad__o(sdram_a[8]), .sdr_a_9__pad__o(sdram_a[9]), .sdr_ba_0__pad__o(sdram_ba[0]), .sdr_ba_1__pad__o(sdram_ba[1]), .sdr_cas_n__pad__o(sdram_cas_n), .sdr_cke__pad__o(sdram_cke), .sdr_clock__pad__o(sdram_clock), .sdr_cs_n__pad__o(sdram_cs_n), .sdr_dm_0__pad__o(sdram_dm[0]), .sdr_dm_1__pad__o(sdram_dm[1]), .sdr_dq_0__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[0]), .sdr_dq_0__pad__o(sdram_dq_o[0]), .sdr_dq_0__pad__oe(sdram_dq_oe[0]), .sdr_dq_10__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[10]), .sdr_dq_10__pad__o(sdram_dq_o[10]), .sdr_dq_10__pad__oe(sdram_dq_oe[10]), .sdr_dq_11__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[11]), .sdr_dq_11__pad__o(sdram_dq_o[11]), .sdr_dq_11__pad__oe(sdram_dq_oe[11]), .sdr_dq_12__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[12]), .sdr_dq_12__pad__o(sdram_dq_o[12]), .sdr_dq_12__pad__oe(sdram_dq_oe[12]), .sdr_dq_13__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[13]), .sdr_dq_13__pad__o(sdram_dq_o[13]), .sdr_dq_13__pad__oe(sdram_dq_oe[13]), .sdr_dq_14__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[14]), .sdr_dq_14__pad__o(sdram_dq_o[14]), .sdr_dq_14__pad__oe(sdram_dq_oe[14]), .sdr_dq_15__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[15]), .sdr_dq_15__pad__o(sdram_dq_o[15]), .sdr_dq_15__pad__oe(sdram_dq_oe[15]), .sdr_dq_1__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[1]), .sdr_dq_1__pad__o(sdram_dq_o[1]), .sdr_dq_1__pad__oe(sdram_dq_oe[1]), .sdr_dq_2__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[2]), .sdr_dq_2__pad__o(sdram_dq_o[2]), .sdr_dq_2__pad__oe(sdram_dq_oe[2]), .sdr_dq_3__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[3]), .sdr_dq_3__pad__o(sdram_dq_o[3]), .sdr_dq_3__pad__oe(sdram_dq_oe[3]), .sdr_dq_4__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[4]), .sdr_dq_4__pad__o(sdram_dq_o[4]), .sdr_dq_4__pad__oe(sdram_dq_oe[4]), .sdr_dq_5__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[5]), .sdr_dq_5__pad__o(sdram_dq_o[5]), .sdr_dq_5__pad__oe(sdram_dq_oe[5]), .sdr_dq_6__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[6]), .sdr_dq_6__pad__o(sdram_dq_o[6]), .sdr_dq_6__pad__oe(sdram_dq_oe[6]), .sdr_dq_7__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[7]), .sdr_dq_7__pad__o(sdram_dq_o[7]), .sdr_dq_7__pad__oe(sdram_dq_oe[7]), .sdr_dq_8__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[8]), .sdr_dq_8__pad__o(sdram_dq_o[8]), .sdr_dq_8__pad__oe(sdram_dq_oe[8]), .sdr_dq_9__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[9]), .sdr_dq_9__pad__o(sdram_dq_o[9]), .sdr_dq_9__pad__oe(sdram_dq_oe[9]), .sdr_ras_n__pad__o(sdram_ras_n), .sdr_we_n__pad__o(sdram_we_n) ); endmodule