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Date: Sat, 16 May 2020 20:07:36 +0000
X-Bugzilla-Reason: CC
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X-Bugzilla-Product: Libre-SOC's first SoC
X-Bugzilla-Component: Source Code
X-Bugzilla-Version: unspecified
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X-Bugzilla-Severity: enhancement
X-Bugzilla-Who: mtnolan2640@gmail.com
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Message-ID: <bug-314-13-7JvqrdCi2V@https.bugs.libre-soc.org/>
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Subject: [libre-riscv-dev] [Bug 314] Create Condition Register pipeline
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