80386 Dependent Features
************************

The i386 version AS supports both the original Intel 386 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture extending the Intel architecture to 64-bits.

Options
=======

The i386 version of AS has a few machine dependent options:

--32 | --64
     Select the word size, either 32 bits or 64 bits. Selecting 32-bit implies Intel i386 architecture, while 64-bit implies AMD x86-64 architecture.

     These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).

-n
     By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi.  This switch disables the optimization.

--divide
     On SVR4-derived platforms, the character / is treated as a comment character, which means that it cannot be used in expressions.  The --divide option turns / into a normal character.  This does not disable / at the beginning of a line starting a comment, or affect using # for starting a comment.

-march=CPU[+EXTENSION...]
     This option specifies the target processor.  The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor.  The following processor names are recognized: i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, k6, k6_2, athlon, opteron, k8, amdfam10, generic32 and generic64.

     In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics.  For example, -march=i686+sse4+vmx extends I686 with SSE4 and VMX.  The following extensions are currently supported: mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4, avx, vmx, smx, xsave, aes, pclmul, fma, movbe, ept, 3dnow, 3dnowa, sse4a, sse5, svme, abm and padlock.

     When the .arch directive is used with -march, the .arch directive will take precedent.

-mtune=CPU
     This option specifies a processor to optimize for. When used in conjunction with the -march option, only instructions of the processor specified by the -march option will be generated.

     Valid CPU values are identical to the processor list of -march=CPU.

-msse2avx
     This option specifies that the assembler should encode SSE instructions with VEX prefix.

-msse-check=NONE

-msse-check=WARNING

-msse-check=ERROR
     These options control if the assembler should check SSE intructions. -msse-check=NONE will make the assembler not to check SSE instructions,  which is the default.  -msse-check=WARNING will make the assembler issue a warning for any SSE intruction. -msse-check=ERROR will make the assembler issue an error for any SSE intruction.

-mmnemonic=ATT

-mmnemonic=INTEL
     This option specifies instruction mnemonic for matching instructions. The .att_mnemonic and .intel_mnemonic directives will take precedent.

-msyntax=ATT

-msyntax=INTEL
     This option specifies instruction syntax when processing instructions. The .att_syntax and .intel_syntax directives will take precedent.

-mnaked-reg
     This opetion specifies that registers don't require a % prefix. The .att_syntax and .intel_syntax directives will take precedent.

x86 specific Directives
=======================

.lcomm SYMBOL , LENGTH[, ALIGNMENT]
     Reserve LENGTH (an absolute expression) bytes for a local common denoted by SYMBOL.  The section and value of SYMBOL are those of the new local common.  The addresses are allocated in the bss section, so that at run-time the bytes start off zeroed.  Since SYMBOL is not declared global, it is normally not visible to LD.  The optional third parameter, ALIGNMENT, specifies the desired alignment of the symbol in the bss section.

     This directive is only available for COFF based x86 targets.

AT&T Syntax versus Intel Syntax
===============================

AS now supports assembly using Intel assembler syntax. .intel_syntax selects Intel mode, and .att_syntax switches back to the usual AT&T mode for compatibility with the output of GCC.  Either of these directives may have an optional argument, prefix, or noprefix specifying whether registers require a % prefix.  AT&T System V/386 assembler syntax is quite different from Intel syntax.  We mention these differences because almost all 80386 documents use Intel syntax.  Notable differences between the two syntaxes are:

  * AT&T immediate operands are preceded by $; Intel immediate operands are undelimited (Intel push 4 is AT&T pushl $4). AT&T register operands are preceded by %; Intel register operands are undelimited.  AT&T absolute (as opposed to PC relative) jump/call operands are prefixed by *; they are undelimited in Intel syntax.

  * AT&T and Intel syntax use the opposite order for source and destination operands.  Intel add eax, 4 is addl $4, %eax.  The source, dest convention is maintained for compatibility with previous Unix assemblers.  Note that bound, invlpga, and instructions with 2 immediate operands, such as the enter instruction, do not have reversed order.  i386-Bugs.

  * In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic.  Mnemonic suffixes of b, w, l and q specify byte (8-bit), word (16-bit), long (32-bit) and quadruple word (64-bit) memory references.  Intel syntax accomplishes this by prefixing memory operands (not the instruction mnemonics) with byte ptr, word ptr, dword ptr and qword ptr.  Thus, Intel mov al, byte ptr FOO is movb FOO, %al in AT&T syntax.

  * Immediate form long jumps and calls are lcall/ljmp $SECTION, $OFFSET in AT&T syntax; the Intel syntax is call/jmp far SECTION:OFFSET.  Also, the far return instruction is lret $STACK-ADJUST in AT&T syntax; Intel syntax is ret far STACK-ADJUST.

  * The AT&T assembler does not provide support for multiple section programs.  Unix style systems expect all programs to be single sections.

Instruction Naming
==================

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands.  The letters b, w, l and q specify byte, word, long and quadruple word operands.  If no suffix is specified by an instruction then AS tries to fill in the missing suffix based on the destination register operand (the last one by convention).  Thus, mov %ax, %bx is equivalent to movw %ax, %bx; also, mov $1, %bx is equivalent to movw $1, bx.  Note that this is incompatible with the AT&T Unix assembler which assumes that a missing mnemonic suffix implies long operand size.  (This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix.)

Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions.  The sign extend and zero extend instructions need two sizes to specify them.  They need a size to sign/zero extend from and a size to zero extend to.  This is accomplished by using two instruction mnemonic suffixes in AT&T syntax.  Base names for sign extend and zero extend are movs... and movz... in AT&T syntax (movsx and movzx in Intel syntax).  The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix.  Thus, movsbl %al, %edx is AT&T syntax for ``move sign extend from %al to %edx.''  Possible suffixes, thus, are bl (from byte to long), bw (from byte to word), wl (from word to long), bq (from byte to quadruple word), wq (from word to quadruple word), and lq (from long to quadruple word).

Different encoding options can be specified via optional mnemonic suffix.  .s suffix swaps 2 register operands in encoding when moving from one register to another.

The Intel-syntax conversion instructions

  * cbw --- sign-extend byte in %al to word in %ax,

  * cwde --- sign-extend word in %ax to long in %eax,

  * cwd --- sign-extend word in %ax to long in %dx:%ax,

  * cdq --- sign-extend dword in %eax to quad in %edx:%eax,

  * cdqe --- sign-extend dword in %eax to quad in %rax (x86-64 only),

  * cqo --- sign-extend quad in %rax to octuple in %rdx:%rax (x86-64 only),

are called cbtw, cwtl, cwtd, cltd, cltq, and cqto in AT&T naming.  AS accepts either naming for these instructions.

Far call/jump instructions are lcall and ljmp in AT&T syntax, but are call far and jump far in Intel convention.

AT&T Mnemonic versus Intel Mnemonic
===================================

AS supports assembly using Intel mnemonic. .intel_mnemonic selects Intel mnemonic with Intel syntax, and .att_mnemonic switches back to the usual AT&T mnemonic with AT&T syntax for compatibility with the output of GCC. Several x87 instructions, fadd, fdiv, fdivp, fdivr, fdivrp, fmul, fsub, fsubp, fsubr and fsubrp,  are implemented in AT&T System V/386 assembler with different mnemonics from those in Intel IA32 specification. GCC generates those instructions with AT&T mnemonic.

Register Naming
===============

Register operands are always prefixed with %.  The 80386 registers consist of

  * the 8 32-bit registers %eax (the accumulator), %ebx, %ecx, %edx, %edi, %esi, %ebp (the frame pointer), and %esp (the stack pointer).

  * the 8 16-bit low-ends of these: %ax, %bx, %cx, %dx, %di, %si, %bp, and %sp.

  * the 8 8-bit registers: %ah, %al, %bh, %bl, %ch, %cl, %dh, and %dl (These are the high-bytes and low-bytes of %ax, %bx, %cx, and %dx)

  * the 6 section registers %cs (code section), %ds (data section), %ss (stack section), %es, %fs, and %gs.

  * the 3 processor control registers %cr0, %cr2, and %cr3.

  * the 6 debug registers %db0, %db1, %db2, %db3, %db6, and %db7.

  * the 2 test registers %tr6 and %tr7.

  * the 8 floating point register stack %st or equivalently %st(0), %st(1), %st(2), %st(3), %st(4), %st(5), %st(6), and %st(7). These registers are overloaded by 8 MMX registers %mm0, %mm1, %mm2, %mm3, %mm4, %mm5, %mm6 and %mm7.

  * the 8 SSE registers registers %xmm0, %xmm1, %xmm2, %xmm3, %xmm4, %xmm5, %xmm6 and %xmm7.

The AMD x86-64 architecture extends the register set by:

  * enhancing the 8 32-bit registers to 64-bit: %rax (the accumulator), %rbx, %rcx, %rdx, %rdi, %rsi, %rbp (the frame pointer), %rsp (the stack pointer)

  * the 8 extended registers %r8--%r15.

  * the 8 32-bit low ends of the extended registers: %r8d--%r15d

  * the 8 16-bit low ends of the extended registers: %r8w--%r15w

  * the 8 8-bit low ends of the extended registers: %r8b--%r15b

  * the 4 8-bit registers: %sil, %dil, %bpl, %spl.

  * the 8 debug registers: %db8--%db15.

  * the 8 SSE registers: %xmm8--%xmm15.

Instruction Prefixes
====================

Instruction prefixes are used to modify the following instruction.  They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to change operand and address sizes. (Most instructions that normally operate on 32-bit operands will use 16-bit operands if the instruction has an ``operand size'' prefix.) Instruction prefixes are best written on the same line as the instruction they act upon. For example, the scas (scan string) instruction is repeated with:

             repne scas %es:(%edi),%al

You may also place prefixes on the lines immediately preceding the instruction, but this circumvents checks that AS does with prefixes, and will not work with all prefixes.

Here is a list of instruction prefixes:

  * Section override prefixes cs, ds, ss, es, fs, gs.  These are automatically added by specifying using the SECTION:MEMORY-OPERAND form for memory references.

  * Operand/Address size prefixes data16 and addr16 change 32-bit operands/addresses into 16-bit operands/addresses, while data32 and addr32 change 16-bit ones (in a .code16 section) into 32-bit operands/addresses.  These prefixes must appear on the same line of code as the instruction they modify. For example, in a 16-bit .code16 section, you might write:

                  addr32 jmpl *(%ebx)

  * The bus lock prefix lock inhibits interrupts during execution of the instruction it precedes.  (This is only valid with certain instructions; see a 80386 manual for details).

  * The wait for coprocessor prefix wait waits for the coprocessor to complete the current instruction.  This should never be needed for the 80386/80387 combination.

  * The rep, repe, and repne prefixes are added to string instructions to make them repeat %ecx times (%cx times if the current address size is 16-bits).

  * The rex family of prefixes is used by x86-64 to encode extensions to i386 instruction set.  The rex prefix has four bits --- an operand size overwrite (64) used to change operand size from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the register set.

     You may write the rex prefixes directly. The rex64xyz instruction emits rex prefix with all the bits set.  By omitting the 64, x, y or z you may write other prefixes as well.  Normally, there is no need to write the prefixes explicitly, since gas will automatically generate them based on the instruction operands.

Memory References
=================

An Intel syntax indirect memory reference of the form

     SECTION:[BASE + INDEX*SCALE + DISP]

is translated into the AT&T syntax

     SECTION:DISP(BASE, INDEX, SCALE)

where BASE and INDEX are the optional 32-bit base and index registers, DISP is the optional displacement, and SCALE, taking the values 1, 2, 4, and 8, multiplies INDEX to calculate the address of the operand.  If no SCALE is specified, SCALE is taken to be 1.  SECTION specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register defaults). Note that section overrides in AT&T syntax must be preceded by a %.  If you specify a section override which coincides with the default section register, AS does not output any section register override prefixes to assemble the given instruction.  Thus, section overrides can be specified to emphasize which section register is used for a given memory operand.

Here are some examples of Intel and AT&T style memory references:

AT&T: -4(%ebp), Intel:  [ebp - 4]
     BASE is %ebp; DISP is -4. SECTION is missing, and the default section is used (%ss for addressing with %ebp as the base register).  INDEX, SCALE are both missing.

AT&T: foo(,%eax,4), Intel: [foo + eax*4]
     INDEX is %eax (scaled by a SCALE 4); DISP is foo.  All other fields are missing.  The section register here defaults to %ds.

AT&T: foo(,1); Intel [foo]
     This uses the value pointed to by foo as a memory operand. Note that BASE and INDEX are both missing, but there is only one ,.  This is a syntactic exception.

AT&T: %gs:foo; Intel gs:foo
     This selects the contents of the variable foo with section register SECTION being %gs.

Absolute (as opposed to PC relative) call and jump operands must be prefixed with *.  If no * is specified, AS always chooses PC relative addressing for jump/call labels.

Any instruction that has a memory operand, but no register operand, must specify its size (byte, word, long, or quadruple) with an instruction mnemonic suffix (b, w, l or q, respectively).

The x86-64 architecture adds an RIP (instruction pointer relative) addressing.  This addressing mode is specified by using rip as a base register.  Only constant offsets are valid. For example:

AT&T: 1234(%rip), Intel: [rip + 1234]
     Points to the address 1234 bytes past the end of the current instruction.

AT&T: symbol(%rip), Intel: [rip + symbol]
     Points to the symbol in RIP relative way, this is shorter than the default absolute addressing.

Other addressing modes remain unchanged in x86-64 architecture, except registers used are 64-bit instead of 32-bit.

Handling of Jump Instructions
=============================

Jump instructions are always optimized to use the smallest possible displacements.  This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close.  If a byte displacement is insufficient a long displacement is used.  We do not support word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction with the data16 instruction prefix), since the 80386 insists upon masking %eip to 16 bits after the word displacement is added. (See also i386-Arch)

Note that the jcxz, jecxz, loop, loopz, loope, loopnz and loopne instructions only come in byte displacements, so that if you use these instructions (GCC does not use them) you may get an error message (and incorrect code).  The AT&T 80386 assembler tries to get around this problem by expanding jcxz foo to

              jcxz cx_zero
              jmp cx_nonzero
     cx_zero: jmp foo
     cx_nonzero:

Floating Point
==============

All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty).  These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each supported type has an instruction mnemonic suffix and a constructor associated with it.  Instruction mnemonic suffixes specify the operand's data type.  Constructors build these data types into memory.

  * Floating point constructors are .float or .single, .double, and .tfloat for 32-, 64-, and 80-bit formats. These correspond to instruction mnemonic suffixes s, l, and t. t stands for 80-bit (ten byte) real.  The 80387 only supports this format via the fldt (load 80-bit real to stack top) and fstpt (store 80-bit real and pop stack) instructions.

  * Integer constructors are .word, .long or .int, and .quad for the 16-, 32-, and 64-bit integer formats.  The corresponding instruction mnemonic suffixes are s (single), l (long), and q (quad).  As with the 80-bit real format, the 64-bit q format is only present in the fildq (load quad integer to stack top) and fistpq (store quad integer and pop stack) instructions.

Register to register operations should not use instruction mnemonic suffixes. fstl %st, %st(1) will give a warning, and be assembled as if you wrote fst %st, %st(1), since all register to register operations use 80-bit floating point operands. (Contrast this with fstl %st, mem, which converts %st from 80-bit to 64-bit floating point format, then stores the result in the 4 byte location mem)

Intel's MMX and AMD's 3DNow! SIMD Operations
============================================

AS supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and probably others.  It also supports AMD's 3DNow! instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future.

Currently, AS does not support Intel's floating point SIMD, Katmai (KNI).

The eight 64-bit MMX operands, also used by 3DNow!, are called %mm0, %mm1, ... %mm7.  They contain eight 8-bit integers, four 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit floating point values.  The MMX registers cannot be used at the same time as the floating point stack.

See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax.

Writing 16-bit Code
===================

While AS normally writes only ``pure'' 32-bit i386 code or 64-bit x86-64 code depending on the default configuration, it also supports writing code to run in real mode or in 16-bit protected mode code segments.  To do this, put a .code16 or .code16gcc directive before the assembly language instructions to be run in 16-bit mode.  You can switch AS back to writing normal 32-bit code with the .code32 directive.

.code16gcc provides experimental support for generating 16-bit code from gcc, and differs from .code16 in that call, ret, enter, leave, push, pop, pusha, popa, pushf, and popf instructions default to 32-bit size.  This is so that the stack pointer is manipulated in the same way over function calls, allowing access to function parameters at the same stack offsets as in 32-bit mode. .code16gcc also automatically adds address size prefixes where necessary to use the 32-bit addressing modes that gcc generates.

The code which AS generates in 16-bit mode will not necessarily run on a 16-bit pre-80386 processor.  To write code that runs on such a processor, you must refrain from using any 32-bit constructs which require AS to output address or operand size prefixes.

Note that writing 16-bit code instructions by explicitly specifying a prefix or an instruction mnemonic suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment.  In a 32-bit code section, the following code generates the machine opcode bytes 66 6a 04, which pushes the value 4 onto the stack, decrementing %esp by 2.

             pushw $4

The same code in a 16-bit code section would generate the machine opcode bytes 6a 04 (i.e., without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section.

AT&T Syntax bugs
================

The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating point instructions with reversed source and destination registers in certain cases.  Unfortunately, gcc and possibly many other programs use this reversed syntax, so we're stuck with it.

For example

             fsub %st,%st(3)

results in %st(3) being updated to %st - %st(3) rather than the expected %st(3) - %st.  This happens with all the non-commutative arithmetic floating point operations with two register operands where the source register is %st and the destination register is %st(i).

Specifying CPU Architecture
===========================

AS may be told to assemble for a particular CPU (sub-)architecture with the .arch CPU_TYPE directive.  This directive enables a warning when gas detects an instruction that is not supported on the CPU specified.  The choices for CPU_TYPE are:

i8086   i186   i286   i386
i486   i586   i686   pentium
pentiumpro   pentiumii   pentiumiii   pentium4
prescott   nocona   core   core2
k6   k6_2   athlon   k8
amdfam10
generic32   generic64
.mmx   .sse   .sse2   .sse3
.ssse3   .sse4.1   .sse4.2   .sse4
.avx   .vmx   .smx   .xsave
.aes   .pclmul   .fma   .movbe
.ept
.3dnow   .3dnowa   .sse4a   .sse5
.svme   .abm
.padlock

Apart from the warning, there are only two other effects on AS operation;  Firstly, if you specify a CPU other than i486, then shift by one instructions such as sarl $1, %eax will automatically use a two byte opcode sequence.  The larger three byte opcode sequence is used on the 486 (and when no architecture is specified) because it executes faster on the 486.  Note that you can explicitly request the two byte opcode by writing sarl %eax. Secondly, if you specify i8086, i186, or i286, and .code16 or .code16gcc then byte offset conditional jumps will be promoted when necessary to a two instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target.

Following the CPU architecture (but not a sub-architecture, which are those starting with a dot), you may specify jumps or nojumps to control automatic promotion of conditional jumps. jumps is the default, and enables jump promotion;  All external jumps will be of the long variety, and file-local jumps will be promoted as necessary. (see i386-Jumps)  nojumps leaves external conditional jumps as byte offset jumps, and warns about file-local conditional jumps that AS promotes. Unconditional jumps are treated as for jumps.

For example

      .arch i8086,nojumps

Notes
=====

There is some trickery concerning the mul and imul instructions that deserves mention.  The 16-, 32-, 64- and 128-bit expanding multiplies (base opcode 0xf6; extension 4 for mul and 5 for imul) can be output only in the one operand form.  Thus, imul %ebx, %eax does not select the expanding multiply; the expanding multiply would clobber the %edx register, and this would confuse GCC output.  Use imul %ebx to get the 64-bit product in %edx:%eax.

We have added a two operand form of imul when the first operand is an immediate mode expression and the second operand is a register. This is just a shorthand, so that, multiplying %eax by 69, for example, can be done with imul $69, %eax rather than imul $69, %eax, %eax.