Constraints for asm Operands
============================

Here are specific details on what constraint letters you can use with asm operands. Constraints can say whether an operand may be in a register, and which kinds of register; whether the operand can be a memory reference, and which kinds of address; whether the operand may be an immediate constant, and which possible values it may have.  Constraints can also require two operands to match. Side-effects aren't allowed in operands of inline asm, unless < or > constraints are used, because there is no guarantee that the side-effects will happen exactly once in an instruction that can update the addressing register.

Simple Constraints
------------------

The simplest kind of constraint is a string full of letters, each of which describes one kind of operand that is permitted.  Here are the letters that are allowed:

whitespace
     Whitespace characters are ignored and can be inserted at any position except the first.  This enables each alternative for different operands to be visually aligned in the machine description even if they have different number of constraints and modifiers.

m
     A memory operand is allowed, with any kind of address that the machine supports in general. Note that the letter used for the general memory constraint can be re-defined by a back end using the TARGET_MEM_CONSTRAINT macro.

o
     A memory operand is allowed, but only if the address is offsettable.  This means that adding a small integer (actually, the width in bytes of the operand, as determined by its machine mode) may be added to the address and the result is also a valid memory address.

     For example, an address which is constant is offsettable; so is an address that is the sum of a register and a constant (as long as a slightly larger constant is also within the range of address-offsets supported by the machine); but an autoincrement or autodecrement address is not offsettable.  More complicated indirect/indexed addresses may or may not be offsettable depending on the other addressing modes that the machine supports.

     Note that in an output operand which can be matched by another operand, the constraint letter o is valid only when accompanied by both < (if the target machine has predecrement addressing) and > (if the target machine has preincrement addressing).

V
     A memory operand that is not offsettable.  In other words, anything that would fit the m constraint but not the o constraint.

<
     A memory operand with autodecrement addressing (either predecrement or postdecrement) is allowed.  In inline asm this constraint is only allowed if the operand is used exactly once in an instruction that can handle the side-effects.  Not using an operand with < in constraint string in the inline asm pattern at all or using it in multiple instructions isn't valid, because the side-effects wouldn't be performed or would be performed more than once.  Furthermore, on some targets the operand with < in constraint string must be accompanied by special instruction suffixes like %U0 instruction suffix on PowerPC or %P0 on IA-64.

>
     A memory operand with autoincrement addressing (either preincrement or postincrement) is allowed.  In inline asm the same restrictions as for < apply.

r
     A register operand is allowed provided that it is in a general register.

i
     An immediate integer operand (one with constant value) is allowed. This includes symbolic constants whose values will be known only at assembly time or later.

n
     An immediate integer operand with a known numeric value is allowed. Many systems cannot support assembly-time constants for operands less than a word wide.  Constraints for these operands should use n rather than i.

I, J, K, ... P
     Other letters in the range I through P may be defined in a machine-dependent fashion to permit immediate integer operands with explicit integer values in specified ranges.  For example, on the 68000, I is defined to stand for the range of values 1 to 8. This is the range permitted as a shift count in the shift instructions.

E
     An immediate floating operand (expression code const_double) is allowed, but only if the target floating point format is the same as that of the host machine (on which the compiler is running).

F
     An immediate floating operand (expression code const_double or const_vector) is allowed.

G, H
     G and H may be defined in a machine-dependent fashion to permit immediate floating operands in particular ranges of values.

s
     An immediate integer operand whose value is not an explicit integer is allowed.

     This might appear strange; if an insn allows a constant operand with a value not known at compile time, it certainly must allow any known value.  So why use s instead of i?  Sometimes it allows better code to be generated.

     For example, on the 68000 in a fullword instruction it is possible to use an immediate operand; but if the immediate value is between -128 and 127, better code results from loading the value into a register and using the register.  This is because the load into the register can be done with a moveq instruction.  We arrange for this to happen by defining the letter K to mean ``any integer outside the range -128 to 127'', and then specifying Ks in the operand constraints.

g
     Any register, memory or immediate integer operand is allowed, except for registers that are not general registers.

X
     Any operand whatsoever is allowed.

0, 1, 2, ... 9
     An operand that matches the specified operand number is allowed.  If a digit is used together with letters within the same alternative, the digit should come last.

     This number is allowed to be more than a single digit.  If multiple digits are encountered consecutively, they are interpreted as a single decimal integer.  There is scant chance for ambiguity, since to-date it has never been desirable that 10 be interpreted as matching either operand 1 or operand 0.  Should this be desired, one can use multiple alternatives instead.

     This is called a matching constraint and what it really means is that the assembler has only a single operand that fills two roles which asm distinguishes.  For example, an add instruction uses two input operands and an output operand, but on most CISC machines an add instruction really has only two operands, one of them an input-output operand:

          addl #35,r12

     Matching constraints are used in these circumstances. More precisely, the two operands that match must include one input-only operand and one output-only operand.  Moreover, the digit must be a smaller number than the number of the operand that uses it in the constraint.

p
     An operand that is a valid memory address is allowed.  This is for ``load address'' and ``push address'' instructions.

     p in the constraint must be accompanied by address_operand as the predicate in the match_operand.  This predicate interprets the mode specified in the match_operand as the mode of the memory reference for which the address would be valid.

OTHER-LETTERS
     Other letters can be defined in machine-dependent fashion to stand for particular classes of registers or other arbitrary operand types. d, a and f are defined on the 68000/68020 to stand for data, address and floating point registers.

Multiple Alternative Constraints
--------------------------------

Sometimes a single instruction has multiple alternative sets of possible operands.  For example, on the 68000, a logical-or instruction can combine register or an immediate value into memory, or it can combine any kind of operand into a register; but it cannot combine one memory location into another.

These constraints are represented as multiple alternatives.  An alternative can be described by a series of letters for each operand.  The overall constraint for an operand is made from the letters for this operand from the first alternative, a comma, the letters for this operand from the second alternative, a comma, and so on until the last alternative.

If all the operands fit any one alternative, the instruction is valid. Otherwise, for each alternative, the compiler counts how many instructions must be added to copy the operands so that that alternative applies. The alternative requiring the least copying is chosen.  If two alternatives need the same amount of copying, the one that comes first is chosen. These choices can be altered with the ? and ! characters:

?
     Disparage slightly the alternative that the ? appears in, as a choice when no alternative applies exactly.  The compiler regards this alternative as one unit more costly for each ? that appears in it.

!
     Disparage severely the alternative that the ! appears in. This alternative can still be used if it fits without reloading, but if reloading is needed, some other alternative will be used.

Constraint Modifier Characters
------------------------------

Here are constraint modifier characters.

=
     Means that this operand is write-only for this instruction: the previous value is discarded and replaced by output data.

+
     Means that this operand is both read and written by the instruction.

     When the compiler fixes up the operands to satisfy the constraints, it needs to know which operands are inputs to the instruction and which are outputs from it.  = identifies an output; + identifies an operand that is both input and output; all other operands are assumed to be input only.

     If you specify = or + in a constraint, you put it in the first character of the constraint string.

&
     Means (in a particular alternative) that this operand is an earlyclobber operand, which is modified before the instruction is finished using the input operands.  Therefore, this operand may not lie in a register that is used as an input operand or as part of any memory address.

     & applies only to the alternative in which it is written.  In constraints with multiple alternatives, sometimes one alternative requires & while others do not.  See, for example, the movdf insn of the 68000.

     An input operand can be tied to an earlyclobber operand if its only use as an input occurs before the early result is written.  Adding alternatives of this form often allows GCC to produce better code when only some of the inputs can be affected by the earlyclobber. See, for example, the mulsi3 insn of the ARM.

     & does not obviate the need to write =.

%
     Declares the instruction to be commutative for this operand and the following operand.  This means that the compiler may interchange the two operands if that is the cheapest way to make all operands fit the constraints. GCC can only handle one commutative pair in an asm; if you use more, the compiler may fail.  Note that you need not use the modifier if the two alternatives are strictly identical; this would only waste time in the reload pass.  The modifier is not operational after register allocation, so the result of define_peephole2 and define_splits performed after reload cannot rely on % to make the intended insn match.

#
     Says that all following characters, up to the next comma, are to be ignored as a constraint.  They are significant only for choosing register preferences.

*
     Says that the following character should be ignored when choosing register preferences.  * has no effect on the meaning of the constraint as a constraint, and no effect on reloading.  For LRA * additionally disparages slightly the alternative if the following character matches the operand.

Constraints for Particular Machines
-----------------------------------

Whenever possible, you should use the general-purpose constraint letters in asm arguments, since they will convey meaning more readily to people reading your code.  Failing that, use the constraint letters that usually have very similar meanings across architectures.  The most commonly used constraints are m and r (for memory and general-purpose registers respectively; see Simple Constraints), and I, usually the letter indicating the most common immediate-constant format.

Each architecture defines additional constraints.  These constraints are used by the compiler itself for instruction generation, as well as for asm statements; therefore, some of the constraints are not particularly useful for asm.  Here is a summary of some of the machine-dependent constraints available on some particular machines; it includes both constraints that are useful for asm and constraints that aren't.  The compiler source file mentioned in the table heading for each architecture is the definitive reference for the meanings of that architecture's constraints.

AArch64 family---config/aarch64/constraints.md

     k
          The stack pointer register (SP)

     w
          Floating point or SIMD vector register

     I
          Integer constant that is valid as an immediate operand in an ADD instruction

     J
          Integer constant that is valid as an immediate operand in a SUB instruction (once negated)

     K
          Integer constant that can be used with a 32-bit logical instruction

     L
          Integer constant that can be used with a 64-bit logical instruction

     M
          Integer constant that is valid as an immediate operand in a 32-bit MOV pseudo instruction. The MOV may be assembled to one of several different machine instructions depending on the value

     N
          Integer constant that is valid as an immediate operand in a 64-bit MOV pseudo instruction

     S
          An absolute symbolic address or a label reference

     Y
          Floating point constant zero

     Z
          Integer constant zero

     Ush
          The high part (bits 12 and upwards) of the pc-relative address of a symbol within 4GB of the instruction

     Q
          A memory address which uses a single base register with no offset

     Ump
          A memory address suitable for a load/store pair instruction in SI, DI, SF and DF modes

ARC ---config/arc/constraints.md

     q
          Registers usable in ARCompact 16-bit instructions: r0-r3, r12-r15.  This constraint can only match when the -mq option is in effect.

     e
          Registers usable as base-regs of memory addresses in ARCompact 16-bit memory instructions: r0-r3, r12-r15, sp. This constraint can only match when the -mq option is in effect.

     D
          ARC FPX (dpfp) 64-bit registers. D0, D1.

     I
          A signed 12-bit integer constant.

     Cal
          constant for arithmetic/logical operations.  This might be any constant that can be put into a long immediate by the assmbler or linker without involving a PIC relocation.

     K
          A 3-bit unsigned integer constant.

     L
          A 6-bit unsigned integer constant.

     CnL
          One's complement of a 6-bit unsigned integer constant.

     CmL
          Two's complement of a 6-bit unsigned integer constant.

     M
          A 5-bit unsigned integer constant.

     O
          A 7-bit unsigned integer constant.

     P
          A 8-bit unsigned integer constant.

     H
          Any const_double value.

ARM family---config/arm/constraints.md

     w
          VFP floating-point register

     G
          The floating-point constant 0.0

     I
          Integer that is valid as an immediate operand in a data processing instruction.  That is, an integer in the range 0 to 255 rotated by a multiple of 2

     J
          Integer in the range -4095 to 4095

     K
          Integer that satisfies constraint I when inverted (ones complement)

     L
          Integer that satisfies constraint I when negated (twos complement)

     M
          Integer in the range 0 to 32

     Q
          A memory reference where the exact address is in a single register (`m' is preferable for asm statements)

     R
          An item in the constant pool

     S
          A symbol in the text segment of the current file

     Uv
          A memory reference suitable for VFP load/store insns (reg+constant offset)

     Uy
          A memory reference suitable for iWMMXt load/store instructions.

     Uq
          A memory reference suitable for the ARMv4 ldrsb instruction.

AVR family---config/avr/constraints.md

     l
          Registers from r0 to r15

     a
          Registers from r16 to r23

     d
          Registers from r16 to r31

     w
          Registers from r24 to r31.  These registers can be used in adiw command

     e
          Pointer register (r26--r31)

     b
          Base pointer register (r28--r31)

     q
          Stack pointer register (SPH:SPL)

     t
          Temporary register r0

     x
          Register pair X (r27:r26)

     y
          Register pair Y (r29:r28)

     z
          Register pair Z (r31:r30)

     I
          Constant greater than -1, less than 64

     J
          Constant greater than -64, less than 1

     K
          Constant integer 2

     L
          Constant integer 0

     M
          Constant that fits in 8 bits

     N
          Constant integer -1

     O
          Constant integer 8, 16, or 24

     P
          Constant integer 1

     G
          A floating point constant 0.0

     Q
          A memory address based on Y or Z pointer with displacement.

Epiphany---config/epiphany/constraints.md

     U16
          An unsigned 16-bit constant.

     K
          An unsigned 5-bit constant.

     L
          A signed 11-bit constant.

     Cm1
          A signed 11-bit constant added to -1. Can only match when the -m1reg-REG option is active.

     Cl1
          Left-shift of -1, i.e., a bit mask with a block of leading ones, the rest being a block of trailing zeroes. Can only match when the -m1reg-REG option is active.

     Cr1
          Right-shift of -1, i.e., a bit mask with a trailing block of ones, the rest being zeroes.  Or to put it another way, one less than a power of two. Can only match when the -m1reg-REG option is active.

     Cal
          Constant for arithmetic/logical operations. This is like i, except that for position independent code, no symbols / expressions needing relocations are allowed.

     Csy
          Symbolic constant for call/jump instruction.

     Rcs
          The register class usable in short insns.  This is a register class constraint, and can thus drive register allocation. This constraint won't match unless -mprefer-short-insn-regs is in effect.

     Rsc
          The the register class of registers that can be used to hold a sibcall call address.  I.e., a caller-saved register.

     Rct
          Core control register class.

     Rgs
          The register group usable in short insns. This constraint does not use a register class, so that it only passively matches suitable registers, and doesn't drive register allocation.

     Rra
          Matches the return address if it can be replaced with the link register.

     Rcc
          Matches the integer condition code register.

     Sra
          Matches the return address if it is in a stack slot.

     Cfm
          Matches control register values to switch fp mode, which are encapsulated in UNSPEC_FP_MODE.

CR16 Architecture---config/cr16/cr16.h

     b
          Registers from r0 to r14 (registers without stack pointer)

     t
          Register from r0 to r11 (all 16-bit registers)

     p
          Register from r12 to r15 (all 32-bit registers)

     I
          Signed constant that fits in 4 bits

     J
          Signed constant that fits in 5 bits

     K
          Signed constant that fits in 6 bits

     L
          Unsigned constant that fits in 4 bits

     M
          Signed constant that fits in 32 bits

     N
          Check for 64 bits wide constants for add/sub instructions

     G
          Floating point constant that is legal for store immediate

Hewlett-Packard PA-RISC---config/pa/pa.h

     a
          General register 1

     f
          Floating point register

     q
          Shift amount register

     x
          Floating point register (deprecated)

     y
          Upper floating point register (32-bit), floating point register (64-bit)

     Z
          Any register

     I
          Signed 11-bit integer constant

     J
          Signed 14-bit integer constant

     K
          Integer constant that can be deposited with a zdepi instruction

     L
          Signed 5-bit integer constant

     M
          Integer constant 0

     N
          Integer constant that can be loaded with a ldil instruction

     O
          Integer constant whose value plus one is a power of 2

     P
          Integer constant that can be used for and operations in depi and extru instructions

     S
          Integer constant 31

     U
          Integer constant 63

     G
          Floating-point constant 0.0

     A
          A lo_sum data-linkage-table memory operand

     Q
          A memory operand that can be used as the destination operand of an integer store instruction

     R
          A scaled or unscaled indexed memory operand

     T
          A memory operand for floating-point loads and stores

     W
          A register indirect memory operand

picoChip family---picochip.h

     k
          Stack register.

     f
          Pointer register.  A register which can be used to access memory without supplying an offset.  Any other register can be used to access memory, but will need a constant offset.  In the case of the offset being zero, it is more efficient to use a pointer register, since this reduces code size.

     t
          A twin register.  A register which may be paired with an adjacent register to create a 32-bit register.

     a
          Any absolute memory address (e.g., symbolic constant, symbolic constant + offset).

     I
          4-bit signed integer.

     J
          4-bit unsigned integer.

     K
          8-bit signed integer.

     M
          Any constant whose absolute value is no greater than 4-bits.

     N
          10-bit signed integer

     O
          16-bit signed integer.

PowerPC and IBM RS6000---config/rs6000/constraints.md

     b
          Address base register

     d
          Floating point register (containing 64-bit value)

     f
          Floating point register (containing 32-bit value)

     v
          Altivec vector register

     wa
          Any VSX register if the -mvsx option was used or NO_REGS.

     wd
          VSX vector register to hold vector double data or NO_REGS.

     wf
          VSX vector register to hold vector float data or NO_REGS.

     wg
          If -mmfpgpr was used, a floating point register or NO_REGS.

     wl
          Floating point register if the LFIWAX instruction is enabled or NO_REGS.

     wm
          VSX register if direct move instructions are enabled, or NO_REGS.

     wn
          No register (NO_REGS).

     wr
          General purpose register if 64-bit instructions are enabled or NO_REGS.

     ws
          VSX vector register to hold scalar double values or NO_REGS.

     wt
          VSX vector register to hold 128 bit integer or NO_REGS.

     wu
          Altivec register to use for float/32-bit int loads/stores  or NO_REGS.

     wv
          Altivec register to use for double loads/stores  or NO_REGS.

     ww
          FP or VSX register to perform float operations under -mvsx or NO_REGS.

     wx
          Floating point register if the STFIWX instruction is enabled or NO_REGS.

     wy
          VSX vector register to hold scalar float values or NO_REGS.

     wz
          Floating point register if the LFIWZX instruction is enabled or NO_REGS.

     wQ
          A memory address that will work with the lq and stq instructions.

     h
          MQ, CTR, or LINK register

     q
          MQ register

     c
          CTR register

     l
          LINK register

     x
          CR register (condition register) number 0

     y
          CR register (condition register)

     z
          XER[CA] carry bit (part of the XER register)

     I
          Signed 16-bit constant

     J
          Unsigned 16-bit constant shifted left 16 bits (use L instead for SImode constants)

     K
          Unsigned 16-bit constant

     L
          Signed 16-bit constant shifted left 16 bits

     M
          Constant larger than 31

     N
          Exact power of 2

     O
          Zero

     P
          Constant whose negation is a signed 16-bit constant

     G
          Floating point constant that can be loaded into a register with one instruction per word

     H
          Integer/Floating point constant that can be loaded into a register using three instructions

     m
          Memory operand. Normally, m does not allow addresses that update the base register. If < or > constraint is also used, they are allowed and therefore on PowerPC targets in that case it is only safe to use m<> in an asm statement if that asm statement accesses the operand exactly once.  The asm statement must also use %U<OPNO> as a placeholder for the ``update'' flag in the corresponding load or store instruction.  For example:

               asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));

          is correct but:

               asm ("st %1,%0" : "=m<>" (mem) : "r" (val));

          is not.

     es
          A ``stable'' memory operand; that is, one which does not include any automodification of the base register.  This used to be useful when m allowed automodification of the base register, but as those are now only allowed when < or > is used, es is basically the same as m without < and >.

     Q
          Memory operand that is an offset from a register (it is usually better to use m or es in asm statements)

     Z
          Memory operand that is an indexed or indirect from a register (it is usually better to use m or es in asm statements)

     R
          AIX TOC entry

     a
          Address operand that is an indexed or indirect from a register (p is preferable for asm statements)

     S
          Constant suitable as a 64-bit mask operand

     T
          Constant suitable as a 32-bit mask operand

     U
          System V Release 4 small data area reference

     t
          AND masks that can be performed by two rldic{l, r} instructions

     W
          Vector constant that does not require memory

     j
          Vector constant that is all zeros.

Intel 386---config/i386/constraints.md

     R
          Legacy register---the eight integer registers available on all i386 processors (a, b, c, d, si, di, bp, sp).

     q
          Any register accessible as Rl.  In 32-bit mode, a, b, c, and d; in 64-bit mode, any integer register.

     Q
          Any register accessible as Rh: a, b, c, and d.

     a
          The a register.

     b
          The b register.

     c
          The c register.

     d
          The d register.

     S
          The si register.

     D
          The di register.

     A
          The a and d registers.  This class is used for instructions that return double word results in the ax:dx register pair.  Single word values will be allocated either in ax or dx. For example on i386 the following implements rdtsc:

               unsigned long long rdtsc (void)
               {
                 unsigned long long tick;
                 __asm__ __volatile__("rdtsc":"=A"(tick));
                 return tick;
               }

          This is not correct on x86_64 as it would allocate tick in either ax or dx.  You have to use the following variant instead:

               unsigned long long rdtsc (void)
               {
                 unsigned int tickl, tickh;
                 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
                 return ((unsigned long long)tickh << 32)|tickl;
               }

     f
          Any 80387 floating-point (stack) register.

     t
          Top of 80387 floating-point stack (%st(0)).

     u
          Second from top of 80387 floating-point stack (%st(1)).

     y
          Any MMX register.

     x
          Any SSE register.

     Yz
          First SSE register (%xmm0).

     I
          Integer constant in the range 0 ... 31, for 32-bit shifts.

     J
          Integer constant in the range 0 ... 63, for 64-bit shifts.

     K
          Signed 8-bit integer constant.

     L
          0xFF or 0xFFFF, for andsi as a zero-extending move.

     M
          0, 1, 2, or 3 (shifts for the lea instruction).

     N
          Unsigned 8-bit integer constant (for in and out instructions).

     G
          Standard 80387 floating point constant.

     C
          Standard SSE floating point constant.

     e
          32-bit signed integer constant, or a symbolic reference known to fit that range (for immediate operands in sign-extending x86-64 instructions).

     Z
          32-bit unsigned integer constant, or a symbolic reference known to fit that range (for immediate operands in zero-extending x86-64 instructions).

Intel IA-64---config/ia64/ia64.h

     a
          General register r0 to r3 for addl instruction

     b
          Branch register

     c
          Predicate register (c as in ``conditional'')

     d
          Application register residing in M-unit

     e
          Application register residing in I-unit

     f
          Floating-point register

     m
          Memory operand.  If used together with < or >, the operand can have postincrement and postdecrement which require printing with %Pn on IA-64.

     G
          Floating-point constant 0.0 or 1.0

     I
          14-bit signed integer constant

     J
          22-bit signed integer constant

     K
          8-bit signed integer constant for logical instructions

     L
          8-bit adjusted signed integer constant for compare pseudo-ops

     M
          6-bit unsigned integer constant for shift counts

     N
          9-bit signed integer constant for load and store postincrements

     O
          The constant zero

     P
          0 or -1 for dep instruction

     Q
          Non-volatile memory for floating-point loads and stores

     R
          Integer constant in the range 1 to 4 for shladd instruction

     S
          Memory operand except postincrement and postdecrement.  This is now roughly the same as m when not used together with < or >.

FRV---config/frv/frv.h

     a
          Register in the class ACC_REGS (acc0 to acc7).

     b
          Register in the class EVEN_ACC_REGS (acc0 to acc7).

     c
          Register in the class CC_REGS (fcc0 to fcc3 and icc0 to icc3).

     d
          Register in the class GPR_REGS (gr0 to gr63).

     e
          Register in the class EVEN_REGS (gr0 to gr63). Odd registers are excluded not in the class but through the use of a machine mode larger than 4 bytes.

     f
          Register in the class FPR_REGS (fr0 to fr63).

     h
          Register in the class FEVEN_REGS (fr0 to fr63). Odd registers are excluded not in the class but through the use of a machine mode larger than 4 bytes.

     l
          Register in the class LR_REG (the lr register).

     q
          Register in the class QUAD_REGS (gr2 to gr63). Register numbers not divisible by 4 are excluded not in the class but through the use of a machine mode larger than 8 bytes.

     t
          Register in the class ICC_REGS (icc0 to icc3).

     u
          Register in the class FCC_REGS (fcc0 to fcc3).

     v
          Register in the class ICR_REGS (cc4 to cc7).

     w
          Register in the class FCR_REGS (cc0 to cc3).

     x
          Register in the class QUAD_FPR_REGS (fr0 to fr63). Register numbers not divisible by 4 are excluded not in the class but through the use of a machine mode larger than 8 bytes.

     z
          Register in the class SPR_REGS (lcr and lr).

     A
          Register in the class QUAD_ACC_REGS (acc0 to acc7).

     B
          Register in the class ACCG_REGS (accg0 to accg7).

     C
          Register in the class CR_REGS (cc0 to cc7).

     G
          Floating point constant zero

     I
          6-bit signed integer constant

     J
          10-bit signed integer constant

     L
          16-bit signed integer constant

     M
          16-bit unsigned integer constant

     N
          12-bit signed integer constant that is negative---i.e. in the range of -2048 to -1

     O
          Constant zero

     P
          12-bit signed integer constant that is greater than zero---i.e. in the range of 1 to 2047.

Blackfin family---config/bfin/constraints.md

     a
          P register

     d
          D register

     z
          A call clobbered P register.

     qN
          A single register.  If N is in the range 0 to 7, the corresponding D register.  If it is A, then the register P0.

     D
          Even-numbered D register

     W
          Odd-numbered D register

     e
          Accumulator register.

     A
          Even-numbered accumulator register.

     B
          Odd-numbered accumulator register.

     b
          I register

     v
          B register

     f
          M register

     c
          Registers used for circular buffering, i.e. I, B, or L registers.

     C
          The CC register.

     t
          LT0 or LT1.

     k
          LC0 or LC1.

     u
          LB0 or LB1.

     x
          Any D, P, B, M, I or L register.

     y
          Additional registers typically used only in prologues and epilogues: RETS, RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.

     w
          Any register except accumulators or CC.

     Ksh
          Signed 16 bit integer (in the range -32768 to 32767)

     Kuh
          Unsigned 16 bit integer (in the range 0 to 65535)

     Ks7
          Signed 7 bit integer (in the range -64 to 63)

     Ku7
          Unsigned 7 bit integer (in the range 0 to 127)

     Ku5
          Unsigned 5 bit integer (in the range 0 to 31)

     Ks4
          Signed 4 bit integer (in the range -8 to 7)

     Ks3
          Signed 3 bit integer (in the range -3 to 4)

     Ku3
          Unsigned 3 bit integer (in the range 0 to 7)

     PN
          Constant N, where N is a single-digit constant in the range 0 to 4.

     PA
          An integer equal to one of the MACFLAG_XXX constants that is suitable for use with either accumulator.

     PB
          An integer equal to one of the MACFLAG_XXX constants that is suitable for use only with accumulator A1.

     M1
          Constant 255.

     M2
          Constant 65535.

     J
          An integer constant with exactly a single bit set.

     L
          An integer constant with all bits set except exactly one.

     H

     Q
          Any SYMBOL_REF.

M32C---config/m32c/m32c.c

     Rsp
     Rfb
     Rsb
          $sp, $fb, $sb.

     Rcr
          Any control register, when they're 16 bits wide (nothing if control registers are 24 bits wide)

     Rcl
          Any control register, when they're 24 bits wide.

     R0w
     R1w
     R2w
     R3w
          $r0, $r1, $r2, $r3.

     R02
          $r0 or $r2, or $r2r0 for 32 bit values.

     R13
          $r1 or $r3, or $r3r1 for 32 bit values.

     Rdi
          A register that can hold a 64 bit value.

     Rhl
          $r0 or $r1 (registers with addressable high/low bytes)

     R23
          $r2 or $r3

     Raa
          Address registers

     Raw
          Address registers when they're 16 bits wide.

     Ral
          Address registers when they're 24 bits wide.

     Rqi
          Registers that can hold QI values.

     Rad
          Registers that can be used with displacements ($a0, $a1, $sb).

     Rsi
          Registers that can hold 32 bit values.

     Rhi
          Registers that can hold 16 bit values.

     Rhc
          Registers chat can hold 16 bit values, including all control registers.

     Rra
          $r0 through R1, plus $a0 and $a1.

     Rfl
          The flags register.

     Rmm
          The memory-based pseudo-registers $mem0 through $mem15.

     Rpi
          Registers that can hold pointers (16 bit registers for r8c, m16c; 24 bit registers for m32cm, m32c).

     Rpa
          Matches multiple registers in a PARALLEL to form a larger register. Used to match function return values.

     Is3
          -8 ... 7

     IS1
          -128 ... 127

     IS2
          -32768 ... 32767

     IU2
          0 ... 65535

     In4
          -8 ... -1 or 1 ... 8

     In5
          -16 ... -1 or 1 ... 16

     In6
          -32 ... -1 or 1 ... 32

     IM2
          -65536 ... -1

     Ilb
          An 8 bit value with exactly one bit set.

     Ilw
          A 16 bit value with exactly one bit set.

     Sd
          The common src/dest memory addressing modes.

     Sa
          Memory addressed using $a0 or $a1.

     Si
          Memory addressed with immediate addresses.

     Ss
          Memory addressed using the stack pointer ($sp).

     Sf
          Memory addressed using the frame base register ($fb).

     Ss
          Memory addressed using the small base register ($sb).

     S1
          $r1h

MeP---config/mep/constraints.md

     a
          The $sp register.

     b
          The $tp register.

     c
          Any control register.

     d
          Either the $hi or the $lo register.

     em
          Coprocessor registers that can be directly loaded ($c0-$c15).

     ex
          Coprocessor registers that can be moved to each other.

     er
          Coprocessor registers that can be moved to core registers.

     h
          The $hi register.

     j
          The $rpc register.

     l
          The $lo register.

     t
          Registers which can be used in $tp-relative addressing.

     v
          The $gp register.

     x
          The coprocessor registers.

     y
          The coprocessor control registers.

     z
          The $0 register.

     A
          User-defined register set A.

     B
          User-defined register set B.

     C
          User-defined register set C.

     D
          User-defined register set D.

     I
          Offsets for $gp-rel addressing.

     J
          Constants that can be used directly with boolean insns.

     K
          Constants that can be moved directly to registers.

     L
          Small constants that can be added to registers.

     M
          Long shift counts.

     N
          Small constants that can be compared to registers.

     O
          Constants that can be loaded into the top half of registers.

     S
          Signed 8-bit immediates.

     T
          Symbols encoded for $tp-rel or $gp-rel addressing.

     U
          Non-constant addresses for loading/saving coprocessor registers.

     W
          The top half of a symbol's value.

     Y
          A register indirect address without offset.

     Z
          Symbolic references to the control bus.

MicroBlaze---config/microblaze/constraints.md

     d
          A general register (r0 to r31).

     z
          A status register (rmsr, $fcc1 to $fcc7).

MIPS---config/mips/constraints.md

     d
          An address register.  This is equivalent to r unless generating MIPS16 code.

     f
          A floating-point register (if available).

     h
          Formerly the hi register.  This constraint is no longer supported.

     l
          The lo register.  Use this register to store values that are no bigger than a word.

     x
          The concatenated hi and lo registers.  Use this register to store doubleword values.

     c
          A register suitable for use in an indirect jump.  This will always be $25 for -mabicalls.

     v
          Register $3.  Do not use this constraint in new code; it is retained only for compatibility with glibc.

     y
          Equivalent to r; retained for backwards compatibility.

     z
          A floating-point condition code register.

     I
          A signed 16-bit constant (for arithmetic instructions).

     J
          Integer zero.

     K
          An unsigned 16-bit constant (for logic instructions).

     L
          A signed 32-bit constant in which the lower 16 bits are zero. Such constants can be loaded using lui.

     M
          A constant that cannot be loaded using lui, addiu or ori.

     N
          A constant in the range -65535 to -1 (inclusive).

     O
          A signed 15-bit constant.

     P
          A constant in the range 1 to 65535 (inclusive).

     G
          Floating-point zero.

     R
          An address that can be used in a non-macro load or store.

     ZC
          When compiling microMIPS code, this constraint matches a memory operand whose address is formed from a base register and a 12-bit offset.  These operands can be used for microMIPS instructions such as ll and sc.  When not compiling for microMIPS code, ZC is equivalent to R.

     ZD
          When compiling microMIPS code, this constraint matches an address operand that is formed from a base register and a 12-bit offset.  These operands can be used for microMIPS instructions such as prefetch.  When not compiling for microMIPS code, ZD is equivalent to p.

Motorola 680x0---config/m68k/constraints.md

     a
          Address register

     d
          Data register

     f
          68881 floating-point register, if available

     I
          Integer in the range 1 to 8

     J
          16-bit signed number

     K
          Signed number whose magnitude is greater than 0x80

     L
          Integer in the range -8 to -1

     M
          Signed number whose magnitude is greater than 0x100

     N
          Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate

     O
          16 (for rotate using swap)

     P
          Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate

     R
          Numbers that mov3q can handle

     G
          Floating point constant that is not a 68881 constant

     S
          Operands that satisfy 'm' when -mpcrel is in effect

     T
          Operands that satisfy 's' when -mpcrel is not in effect

     Q
          Address register indirect addressing mode

     U
          Register offset addressing

     W
          const_call_operand

     Cs
          symbol_ref or const

     Ci
          const_int

     C0
          const_int 0

     Cj
          Range of signed numbers that don't fit in 16 bits

     Cmvq
          Integers valid for mvq

     Capsw
          Integers valid for a moveq followed by a swap

     Cmvz
          Integers valid for mvz

     Cmvs
          Integers valid for mvs

     Ap
          push_operand

     Ac
          Non-register operands allowed in clr

Moxie---config/moxie/constraints.md

     A
          An absolute address

     B
          An offset address

     W
          A register indirect memory operand

     I
          A constant in the range of 0 to 255.

     N
          A constant in the range of 0 to -255.

MSP430--config/msp430/constraints.md

     R12
          Register R12.

     R13
          Register R13.

     K
          Integer constant 1.

     L
          Integer constant -1^20..1^19.

     M
          Integer constant 1-4.

     Ya
          Memory references which do not require an extended MOVX instruction.

     Yl
          Memory reference, labels only.

     Ys
          Memory reference, stack only.

NDS32---config/nds32/constraints.md

     w
          LOW register class $r0 to $r7 constraint for V3/V3M ISA.

     l
          LOW register class $r0 to $r7.

     d
          MIDDLE register class $r0 to $r11, $r16 to $r19.

     h
          HIGH register class $r12 to $r14, $r20 to $r31.

     t
          Temporary assist register $ta (i.e. $r15).

     k
          Stack register $sp.

     Iu03
          Unsigned immediate 3-bit value.

     In03
          Negative immediate 3-bit value in the range of -7--0.

     Iu04
          Unsigned immediate 4-bit value.

     Is05
          Signed immediate 5-bit value.

     Iu05
          Unsigned immediate 5-bit value.

     In05
          Negative immediate 5-bit value in the range of -31--0.

     Ip05
          Unsigned immediate 5-bit value for movpi45 instruction with range 16--47.

     Iu06
          Unsigned immediate 6-bit value constraint for addri36.sp instruction.

     Iu08
          Unsigned immediate 8-bit value.

     Iu09
          Unsigned immediate 9-bit value.

     Is10
          Signed immediate 10-bit value.

     Is11
          Signed immediate 11-bit value.

     Is15
          Signed immediate 15-bit value.

     Iu15
          Unsigned immediate 15-bit value.

     Ic15
          A constant which is not in the range of imm15u but ok for bclr instruction.

     Ie15
          A constant which is not in the range of imm15u but ok for bset instruction.

     It15
          A constant which is not in the range of imm15u but ok for btgl instruction.

     Ii15
          A constant whose compliment value is in the range of imm15u and ok for bitci instruction.

     Is16
          Signed immediate 16-bit value.

     Is17
          Signed immediate 17-bit value.

     Is19
          Signed immediate 19-bit value.

     Is20
          Signed immediate 20-bit value.

     Ihig
          The immediate value that can be simply set high 20-bit.

     Izeb
          The immediate value 0xff.

     Izeh
          The immediate value 0xffff.

     Ixls
          The immediate value 0x01.

     Ix11
          The immediate value 0x7ff.

     Ibms
          The immediate value with power of 2.

     Ifex
          The immediate value with power of 2 minus 1.

     U33
          Memory constraint for 333 format.

     U45
          Memory constraint for 45 format.

     U37
          Memory constraint for 37 format.

Nios II family---config/nios2/constraints.md

     I
          Integer that is valid as an immediate operand in an instruction taking a signed 16-bit number. Range -32768 to 32767.

     J
          Integer that is valid as an immediate operand in an instruction taking an unsigned 16-bit number. Range 0 to 65535.

     K
          Integer that is valid as an immediate operand in an instruction taking only the upper 16-bits of a 32-bit number. Range 32-bit numbers with the lower 16-bits being 0.

     L
          Integer that is valid as an immediate operand for a shift instruction. Range 0 to 31.

     M
          Integer that is valid as an immediate operand for only the value 0. Can be used in conjunction with the format modifier z to use r0 instead of 0 in the assembly output.

     N
          Integer that is valid as an immediate operand for a custom instruction opcode. Range 0 to 255.

     S
          Matches immediates which are addresses in the small data section and therefore can be added to gp as a 16-bit immediate to re-create their 32-bit value.

PDP-11---config/pdp11/constraints.md

     a
          Floating point registers AC0 through AC3.  These can be loaded from/to memory with a single instruction.

     d
          Odd numbered general registers (R1, R3, R5).  These are used for 16-bit multiply operations.

     f
          Any of the floating point registers (AC0 through AC5).

     G
          Floating point constant 0.

     I
          An integer constant that fits in 16 bits.

     J
          An integer constant whose low order 16 bits are zero.

     K
          An integer constant that does not meet the constraints for codes I or J.

     L
          The integer constant 1.

     M
          The integer constant -1.

     N
          The integer constant 0.

     O
          Integer constants -4 through -1 and 1 through 4; shifts by these amounts are handled as multiple single-bit shifts rather than a single variable-length shift.

     Q
          A memory reference which requires an additional word (address or offset) after the opcode.

     R
          A memory reference that is encoded within the opcode.

RL78---config/rl78/constraints.md

     Int3
          An integer constant in the range 1 ... 7.

     Int8
          An integer constant in the range 0 ... 255.

     J
          An integer constant in the range -255 ... 0

     K
          The integer constant 1.

     L
          The integer constant -1.

     M
          The integer constant 0.

     N
          The integer constant 2.

     O
          The integer constant -2.

     P
          An integer constant in the range 1 ... 15.

     Qbi
          The built-in compare types--eq, ne, gtu, ltu, geu, and leu.

     Qsc
          The synthetic compare types--gt, lt, ge, and le.

     Wab
          A memory reference with an absolute address.

     Wbc
          A memory reference using BC as a base register, with an optional offset.

     Wca
          A memory reference using AX, BC, DE, or HL for the address, for calls.

     Wcv
          A memory reference using any 16-bit register pair for the address, for calls.

     Wd2
          A memory reference using DE as a base register, with an optional offset.

     Wde
          A memory reference using DE as a base register, without any offset.

     Wfr
          Any memory reference to an address in the far address space.

     Wh1
          A memory reference using HL as a base register, with an optional one-byte offset.

     Whb
          A memory reference using HL as a base register, with B or C as the index register.

     Whl
          A memory reference using HL as a base register, without any offset.

     Ws1
          A memory reference using SP as a base register, with an optional one-byte offset.

     Y
          Any memory reference to an address in the near address space.

     A
          The AX register.

     B
          The BC register.

     D
          The DE register.

     R
          A through L registers.

     S
          The SP register.

     T
          The HL register.

     Z08W
          The 16-bit R8 register.

     Z10W
          The 16-bit R10 register.

     Zint
          The registers reserved for interrupts (R24 to R31).

     a
          The A register.

     b
          The B register.

     c
          The C register.

     d
          The D register.

     e
          The E register.

     h
          The H register.

     l
          The L register.

     v
          The virtual registers.

     w
          The PSW register.

     x
          The X register.

RX---config/rx/constraints.md

     Q
          An address which does not involve register indirect addressing or pre/post increment/decrement addressing.

     Symbol
          A symbol reference.

     Int08
          A constant in the range -256 to 255, inclusive.

     Sint08
          A constant in the range -128 to 127, inclusive.

     Sint16
          A constant in the range -32768 to 32767, inclusive.

     Sint24
          A constant in the range -8388608 to 8388607, inclusive.

     Uint04
          A constant in the range 0 to 15, inclusive.

SPARC---config/sparc/sparc.h

     f
          Floating-point register on the SPARC-V8 architecture and lower floating-point register on the SPARC-V9 architecture.

     e
          Floating-point register.  It is equivalent to f on the SPARC-V8 architecture and contains both lower and upper floating-point registers on the SPARC-V9 architecture.

     c
          Floating-point condition code register.

     d
          Lower floating-point register.  It is only valid on the SPARC-V9 architecture when the Visual Instruction Set is available.

     b
          Floating-point register.  It is only valid on the SPARC-V9 architecture when the Visual Instruction Set is available.

     h
          64-bit global or out register for the SPARC-V8+ architecture.

     C
          The constant all-ones, for floating-point.

     A
          Signed 5-bit constant

     D
          A vector constant

     I
          Signed 13-bit constant

     J
          Zero

     K
          32-bit constant with the low 12 bits clear (a constant that can be loaded with the sethi instruction)

     L
          A constant in the range supported by movcc instructions (11-bit signed immediate)

     M
          A constant in the range supported by movrcc instructions (10-bit signed immediate)

     N
          Same as K, except that it verifies that bits that are not in the lower 32-bit range are all zero.  Must be used instead of K for modes wider than SImode

     O
          The constant 4096

     G
          Floating-point zero

     H
          Signed 13-bit constant, sign-extended to 32 or 64 bits

     P
          The constant -1

     Q
          Floating-point constant whose integral representation can be moved into an integer register using a single sethi instruction

     R
          Floating-point constant whose integral representation can be moved into an integer register using a single mov instruction

     S
          Floating-point constant whose integral representation can be moved into an integer register using a high/lo_sum instruction sequence

     T
          Memory address aligned to an 8-byte boundary

     U
          Even register

     W
          Memory address for e constraint registers

     w
          Memory address with only a base register

     Y
          Vector zero

SPU---config/spu/spu.h

     a
          An immediate which can be loaded with the il/ila/ilh/ilhu instructions.  const_int is treated as a 64 bit value.

     c
          An immediate for and/xor/or instructions.  const_int is treated as a 64 bit value.

     d
          An immediate for the iohl instruction.  const_int is treated as a 64 bit value.

     f
          An immediate which can be loaded with fsmbi.

     A
          An immediate which can be loaded with the il/ila/ilh/ilhu instructions.  const_int is treated as a 32 bit value.

     B
          An immediate for most arithmetic instructions.  const_int is treated as a 32 bit value.

     C
          An immediate for and/xor/or instructions.  const_int is treated as a 32 bit value.

     D
          An immediate for the iohl instruction.  const_int is treated as a 32 bit value.

     I
          A constant in the range [-64, 63] for shift/rotate instructions.

     J
          An unsigned 7-bit constant for conversion/nop/channel instructions.

     K
          A signed 10-bit constant for most arithmetic instructions.

     M
          A signed 16 bit immediate for stop.

     N
          An unsigned 16-bit constant for iohl and fsmbi.

     O
          An unsigned 7-bit constant whose 3 least significant bits are 0.

     P
          An unsigned 3-bit constant for 16-byte rotates and shifts

     R
          Call operand, reg, for indirect calls

     S
          Call operand, symbol, for relative calls.

     T
          Call operand, const_int, for absolute calls.

     U
          An immediate which can be loaded with the il/ila/ilh/ilhu instructions.  const_int is sign extended to 128 bit.

     W
          An immediate for shift and rotate instructions.  const_int is treated as a 32 bit value.

     Y
          An immediate for and/xor/or instructions.  const_int is sign extended as a 128 bit.

     Z
          An immediate for the iohl instruction.  const_int is sign extended to 128 bit.

S/390 and zSeries---config/s390/s390.h

     a
          Address register (general purpose register except r0)

     c
          Condition code register

     d
          Data register (arbitrary general purpose register)

     f
          Floating-point register

     I
          Unsigned 8-bit constant (0--255)

     J
          Unsigned 12-bit constant (0--4095)

     K
          Signed 16-bit constant (-32768--32767)

     L
          Value appropriate as displacement.

          (0..4095)
               for short displacement

          (-524288..524287)
               for long displacement

     M
          Constant integer with a value of 0x7fffffff.

     N
          Multiple letter constraint followed by 4 parameter letters.

          0..9:
               number of the part counting from most to least significant

          H,Q:
               mode of the part

          D,S,H:
               mode of the containing operand

          0,F:
               value of the other parts (F---all bits set)

          The constraint matches if the specified part of a constant has a value different from its other parts.

     Q
          Memory reference without index register and with short displacement.

     R
          Memory reference with index register and short displacement.

     S
          Memory reference without index register but with long displacement.

     T
          Memory reference with index register and long displacement.

     U
          Pointer with short displacement.

     W
          Pointer with long displacement.

     Y
          Shift count operand.

Score family---config/score/score.h

     d
          Registers from r0 to r32.

     e
          Registers from r0 to r16.

     t
          r8---r11 or r22---r27 registers.

     h
          hi register.

     l
          lo register.

     x
          hi + lo register.

     q
          cnt register.

     y
          lcb register.

     z
          scb register.

     a
          cnt + lcb + scb register.

     c
          cr0---cr15 register.

     b
          cp1 registers.

     f
          cp2 registers.

     i
          cp3 registers.

     j
          cp1 + cp2 + cp3 registers.

     I
          High 16-bit constant (32-bit constant with 16 LSBs zero).

     J
          Unsigned 5 bit integer (in the range 0 to 31).

     K
          Unsigned 16 bit integer (in the range 0 to 65535).

     L
          Signed 16 bit integer (in the range -32768 to 32767).

     M
          Unsigned 14 bit integer (in the range 0 to 16383).

     N
          Signed 14 bit integer (in the range -8192 to 8191).

     Z
          Any SYMBOL_REF.

Xstormy16---config/stormy16/stormy16.h

     a
          Register r0.

     b
          Register r1.

     c
          Register r2.

     d
          Register r8.

     e
          Registers r0 through r7.

     t
          Registers r0 and r1.

     y
          The carry register.

     z
          Registers r8 and r9.

     I
          A constant between 0 and 3 inclusive.

     J
          A constant that has exactly one bit set.

     K
          A constant that has exactly one bit clear.

     L
          A constant between 0 and 255 inclusive.

     M
          A constant between -255 and 0 inclusive.

     N
          A constant between -3 and 0 inclusive.

     O
          A constant between 1 and 4 inclusive.

     P
          A constant between -4 and -1 inclusive.

     Q
          A memory reference that is a stack push.

     R
          A memory reference that is a stack pop.

     S
          A memory reference that refers to a constant address of known value.

     T
          The register indicated by Rx (not implemented yet).

     U
          A constant that is not between 2 and 15 inclusive.

     Z
          The constant 0.

TI C6X family---config/c6x/constraints.md

     a
          Register file A (A0--A31).

     b
          Register file B (B0--B31).

     A
          Predicate registers in register file A (A0--A2 on C64X and higher, A1 and A2 otherwise).

     B
          Predicate registers in register file B (B0--B2).

     C
          A call-used register in register file B (B0--B9, B16--B31).

     Da
          Register file A, excluding predicate registers (A3--A31, plus A0 if not C64X or higher).

     Db
          Register file B, excluding predicate registers (B3--B31).

     Iu4
          Integer constant in the range 0 ... 15.

     Iu5
          Integer constant in the range 0 ... 31.

     In5
          Integer constant in the range -31 ... 0.

     Is5
          Integer constant in the range -16 ... 15.

     I5x
          Integer constant that can be the operand of an ADDA or a SUBA insn.

     IuB
          Integer constant in the range 0 ... 65535.

     IsB
          Integer constant in the range -32768 ... 32767.

     IsC
          Integer constant in the range -2^20 ... 2^20 - 1.

     Jc
          Integer constant that is a valid mask for the clr instruction.

     Js
          Integer constant that is a valid mask for the set instruction.

     Q
          Memory location with A base register.

     R
          Memory location with B base register.

     Z
          Register B14 (aka DP).

TILE-Gx---config/tilegx/constraints.md

     R00
     R01
     R02
     R03
     R04
     R05
     R06
     R07
     R08
     R09
     R10
          Each of these represents a register constraint for an individual register, from r0 to r10.

     I
          Signed 8-bit integer constant.

     J
          Signed 16-bit integer constant.

     K
          Unsigned 16-bit integer constant.

     L
          Integer constant that fits in one signed byte when incremented by one (-129 ... 126).

     m
          Memory operand.  If used together with < or >, the operand can have postincrement which requires printing with %In and %in on TILE-Gx.  For example:

               asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));

     M
          A bit mask suitable for the BFINS instruction.

     N
          Integer constant that is a byte tiled out eight times.

     O
          The integer zero constant.

     P
          Integer constant that is a sign-extended byte tiled out as four shorts.

     Q
          Integer constant that fits in one signed byte when incremented (-129 ... 126), but excluding -1.

     S
          Integer constant that has all 1 bits consecutive and starting at bit 0.

     T
          A 16-bit fragment of a got, tls, or pc-relative reference.

     U
          Memory operand except postincrement.  This is roughly the same as m when not used together with < or >.

     W
          An 8-element vector constant with identical elements.

     Y
          A 4-element vector constant with identical elements.

     Z0
          The integer constant 0xffffffff.

     Z1
          The integer constant 0xffffffff00000000.

TILEPro---config/tilepro/constraints.md

     R00
     R01
     R02
     R03
     R04
     R05
     R06
     R07
     R08
     R09
     R10
          Each of these represents a register constraint for an individual register, from r0 to r10.

     I
          Signed 8-bit integer constant.

     J
          Signed 16-bit integer constant.

     K
          Nonzero integer constant with low 16 bits zero.

     L
          Integer constant that fits in one signed byte when incremented by one (-129 ... 126).

     m
          Memory operand.  If used together with < or >, the operand can have postincrement which requires printing with %In and %in on TILEPro.  For example:

               asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));

     M
          A bit mask suitable for the MM instruction.

     N
          Integer constant that is a byte tiled out four times.

     O
          The integer zero constant.

     P
          Integer constant that is a sign-extended byte tiled out as two shorts.

     Q
          Integer constant that fits in one signed byte when incremented (-129 ... 126), but excluding -1.

     T
          A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative reference.

     U
          Memory operand except postincrement.  This is roughly the same as m when not used together with < or >.

     W
          A 4-element vector constant with identical elements.

     Y
          A 2-element vector constant with identical elements.

Xtensa---config/xtensa/constraints.md

     a
          General-purpose 32-bit register

     b
          One-bit boolean register

     A
          MAC16 40-bit accumulator register

     I
          Signed 12-bit integer constant, for use in MOVI instructions

     J
          Signed 8-bit integer constant, for use in ADDI instructions

     K
          Integer constant valid for BccI instructions

     L
          Unsigned constant valid for BccUI instructions