# Instruction Synchronise XL-Form * isync Pseudo-code: # TODO undefined(0) Special Registers Altered: None # Synchronise XL-Form * sync L2 Pseudo-code: # TODO undefined(0) Special Registers Altered: None # Load Byte And Reserve Indexed X-Form * lbarx RT,RA,RB,EH Pseudo-code: EA <- (RA|0) + (RB) RESERVE <- 1 RESERVE_LENGTH <- 1 RESERVE_ADDR <- real_addr(EA) RT <- [0]*56 || MEM(EA, 1) Special Registers Altered: None # Load Halfword And Reserve Indexed X-Form * lharx RT,RA,RB,EH Pseudo-code: EA <- (RA|0) + (RB) RESERVE <- 1 RESERVE_LENGTH <- 2 RESERVE_ADDR <- real_addr(EA) RT <- [0]*48 || MEM(EA, 2) Special Registers Altered: None # Load Word And Reserve Indexed X-Form * lwarx RT,RA,RB,EH Pseudo-code: EA <- (RA|0) + (RB) RESERVE <- 1 RESERVE_LENGTH <- 4 RESERVE_ADDR <- real_addr(EA) RT <- [0]*32 || MEM(EA, 4) Special Registers Altered: None # Load Doubleword And Reserve Indexed X-Form * ldarx RT,RA,RB,EH Pseudo-code: EA <- (RA|0) + (RB) RESERVE <- 1 RESERVE_LENGTH <- 8 RESERVE_ADDR <- real_addr(EA) RT <- MEM(EA, 8) Special Registers Altered: None # Load Quadword And Reserve Indexed X-Form * lqarx RTp,RA,RB,EH Pseudo-code: EA <- (RA|0) + (RB) RESERVE <- 1 RESERVE_LENGTH <- 16 RESERVE_ADDR <- real_addr(EA) RTp <- MEM(EA, 16) Special Registers Altered: None # Store Byte Conditional Indexed X-Form * stbcx. RS,RA,RB Pseudo-code: EA <- (RA|0) + (RB) undefined_case <- 0 store_performed <- 0b0 if RESERVE then if ((RESERVE_LENGTH = 1) & (RESERVE_ADDR = real_addr(EA))) then MEM(EA, 1) <- (RS)[56:63] undefined_case <- 0 store_performed <- 0b1 else # set z to smallest real page size supported by implementation z <- REAL_PAGE_SIZE if (RESERVE_ADDR / z) = (real_addr(EA) / z) then undefined_case <- 1 else undefined_case <- 0 store_performed <- 0b0 else undefined_case <- 0 store_performed <- 0b0 if undefined_case then u1 <- undefined(0b1) if u1 then MEM(EA, 1) <- (RS)[56:63] u2 <- undefined(0b1) CR0 <- 0b00 || u2 || XER[SO] else CR0 <- 0b00 || store_performed || XER[SO] RESERVE <- 0 Special Registers Altered: CR0 # Store Halfword Conditional Indexed X-Form * sthcx. RS,RA,RB Pseudo-code: EA <- (RA|0) + (RB) undefined_case <- 0 store_performed <- 0b0 if RESERVE then if ((RESERVE_LENGTH = 2) & (RESERVE_ADDR = real_addr(EA))) then MEM(EA, 2) <- (RS)[48:63] undefined_case <- 0 store_performed <- 0b1 else # set z to smallest real page size supported by implementation z <- REAL_PAGE_SIZE if (RESERVE_ADDR / z) = (real_addr(EA) / z) then undefined_case <- 1 else undefined_case <- 0 store_performed <- 0b0 else undefined_case <- 0 store_performed <- 0b0 if undefined_case then u1 <- undefined(0b1) if u1 then MEM(EA, 2) <- (RS)[48:63] u2 <- undefined(0b1) CR0 <- 0b00 || u2 || XER[SO] else CR0 <- 0b00 || store_performed || XER[SO] RESERVE <- 0 Special Registers Altered: CR0 # Store word Conditional Indexed X-Form * stwcx. RS,RA,RB Pseudo-code: EA <- (RA|0) + (RB) undefined_case <- 0 store_performed <- 0b0 if RESERVE then if ((RESERVE_LENGTH = 4) & (RESERVE_ADDR = real_addr(EA))) then MEM(EA, 4) <- (RS)[32:63] undefined_case <- 0 store_performed <- 0b1 else # set z to smallest real page size supported by implementation z <- REAL_PAGE_SIZE if (RESERVE_ADDR / z) = (real_addr(EA) / z) then undefined_case <- 1 else undefined_case <- 0 store_performed <- 0b0 else undefined_case <- 0 store_performed <- 0b0 if undefined_case then u1 <- undefined(0b1) if u1 then MEM(EA, 4) <- (RS)[32:63] u2 <- undefined(0b1) CR0 <- 0b00 || u2 || XER[SO] else CR0 <- 0b00 || store_performed || XER[SO] RESERVE <- 0 Special Registers Altered: CR0 # Store Doubleword Conditional Indexed X-Form * stdcx. RS,RA,RB Pseudo-code: EA <- (RA|0) + (RB) undefined_case <- 0 store_performed <- 0b0 if RESERVE then if ((RESERVE_LENGTH = 8) & (RESERVE_ADDR = real_addr(EA))) then MEM(EA, 8) <- (RS) undefined_case <- 0 store_performed <- 0b1 else # set z to smallest real page size supported by implementation z <- REAL_PAGE_SIZE if (RESERVE_ADDR / z) = (real_addr(EA) / z) then undefined_case <- 1 else undefined_case <- 0 store_performed <- 0b0 else undefined_case <- 0 store_performed <- 0b0 if undefined_case then u1 <- undefined(0b1) if u1 then MEM(EA, 8) <- (RS) u2 <- undefined(0b1) CR0 <- 0b00 || u2 || XER[SO] else CR0 <- 0b00 || store_performed || XER[SO] RESERVE <- 0 Special Registers Altered: CR0 # Store Quadword Conditional Indexed X-Form * stqcx. RSp,RA,RB Pseudo-code: EA <- (RA|0) + (RB) undefined_case <- 0 store_performed <- 0b0 if RESERVE then if ((RESERVE_LENGTH = 16) & (RESERVE_ADDR = real_addr(EA))) then MEM(EA, 16) <- (RSp) undefined_case <- 0 store_performed <- 0b1 else # set z to smallest real page size supported by implementation z <- REAL_PAGE_SIZE if (RESERVE_ADDR / z) = (real_addr(EA) / z) then undefined_case <- 1 else undefined_case <- 0 store_performed <- 0b0 else undefined_case <- 0 store_performed <- 0b0 if undefined_case then u1 <- undefined(0b1) if u1 then MEM(EA, 16) <- (RSp) u2 <- undefined(0b1) CR0 <- 0b00 || u2 || XER[SO] else CR0 <- 0b00 || store_performed || XER[SO] RESERVE <- 0 Special Registers Altered: CR0