# Store Byte with Update D-Form * stbup RS,D(RA) Pseudo-code: EA <- (RA) + EXTS(D) ea <- (RA) MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1] RA <- EA Description: Let the effective address (EA) be the sum (RA)+ D. (RS)[56:63] are stored into the byte in storage addressed by EA. EA is placed into register RA. If RA=0, the instruction form is invalid. Special Registers Altered: None # Store Byte with Update Indexed X-Form * stbupx RS,RA,RB Pseudo-code: EA <- (RA) + (RB) ea <- (RA) MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1] RA <- EA Description: Let the effective address (EA) be the sum (RA)+ (RB). (RS)[56:63] are stored into the byte in storage addressed by EA. EA is placed into register RA. If RA=0, the instruction form is invalid. Special Registers Altered: None # Store Halfword with Update D-Form * sthup RS,D(RA) Pseudo-code: EA <- (RA) + EXTS(D) ea <- (RA) MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1] RA <- EA Special Registers Altered: None # Store Halfword with Update Indexed X-Form * sthupx RS,RA,RB Pseudo-code: EA <- (RA) + (RB) ea <- (RA) MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1] RA <- EA Special Registers Altered: None # Store Word with Update D-Form * stwup RS,D(RA) Pseudo-code: EA <- (RA) + EXTS(D) ea <- (RA) MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1] RA <- EA Special Registers Altered: None # Store Word with Update Indexed X-Form * stwupx RS,RA,RB Pseudo-code: EA <- (RA) + (RB) ea <- (RA) MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1] RA <- EA Special Registers Altered: None # Store Doubleword with Update DS-Form * stdup RS,DS(RA) Pseudo-code: EA <- (RA) + EXTS(DS || 0b00) ea <- (RA) MEM(ea, 8) <- (RS) RA <- EA Special Registers Altered: None # Store Doubleword with Update Indexed X-Form * stdupx RS,RA,RB Pseudo-code: EA <- (RA) + (RB) ea <- (RA) MEM(ea, 8) <- (RS) RA <- EA Special Registers Altered: None