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# Load Floating-Point Single with Post-Update Shifted Indexed

Z23-Form

* lfsupsx FRT,RA,RB,SH

Pseudo-code:

    EA <- (RA) + (RB)<<(SH+1)
    FRT <- DOUBLE(MEM(RA, 4))
    RA <- EA

Description:

    Let the effective address (EA) be the sum of the contents of
    register RB shifted by (SH+1), and the contents of register RA.

    The word in storage addressed by EA is interpreted as
    a floating-point single-precision operand. This word is
    converted to floating-point double format (see
    page 138) and placed into register FRT.

    EA is placed into register RA.

    If RA=0, the instruction form is invalid.

Special Registers Altered:

    None

# Load Floating-Point Double with Post-Update Shifted Indexed

Z23-Form

* lfdupsx FRT,RA,RB,SH

Pseudo-code:

    EA <- (RA) + (RB)<<(SH+1)
    FRT <- MEM(RA, 8)
    RA <- EA

Description:

    Let the effective address (EA) be the sum of the contents of
    register RB shifted by (SH+1), and the contents of register RA.

    The doubleword in storage addressed by EA is loaded
    into register FRT.

    EA is placed into register RA.

    If RA=0, the instruction form is invalid.

Special Registers Altered:

    None