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\date{}

\begin{document}

\chapter*{Preamble}
\addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}

\textbf{Last modified date: \today}

This document is an auto-generated version of the Draft SVP64
Specification available at

\begin{verbatim}
     https://libre-soc.org/openpower/sv
\end{verbatim}

for which the source code is available at

\begin{verbatim}
     https://git.libre-soc.org/?p=libreriscv.git;a=tree;f=openpower;hb=HEAD
\end{verbatim}

This PDF may be created with "make pdf" from the following file:

\begin{verbatim}
    https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/Makefile;hb=HEAD
\end{verbatim}

by executing the following commands:

\begin{verbatim}
    git clone https://git.libre-soc.org/git/libreriscv.git libresoc
    cd libresoc/libresoc/openpower
    make pdf
\end{verbatim}

Simple-V Cray-style Vectors have been developed by the Libre-SOC Team,
sponsored by the NLnet Foundation and NGI POINTER under
EU Grants 871528 and 957073.

Simple-V is in DRAFT Status and will be submitted publicly
(non-confidentially) through the OPF ISA WG "External Submissions"
Process. Funding from NLnet, through their Privacy and Enhanced Trust
Programme, requires full transparency.

As this document is under continuous rapid revision please check frequently
at:

\begin{verbatim}
    https://ftp.libre-soc.org/simple_v_spec.pdf
\end{verbatim}

\subsection*{Contacts}
For questions, comments, and clarification, please contact the following:
\begin{itemize}
    \itemsep -0.3em
    \item Libre-SOC ISA Dev Mailing List - libre-soc-isa@lists.libre-soc.org
    \item Luke Kenneth Casson Leighton - Libre-SOC team lead and Red 
    Semiconductor Ltd Director - lkcl@lkcl.net
    \item David Calderwood - Red Semiconductor Ltd Director - 
    djac@calderwoodhan.com
    \item Toshaan Bharvani - OpenPOWER Foundation Technical Chair, VanTosh 
    Director - toshaan@vantosh.com
    \item Konstantinos Margaritis -  Engineer and Founder of VectorCamp, writing optimised assembler for a number of SIMD/Vector ISAs  - konstantinos@vectorcamp.gr
    \item Dmitry Selyutin - Libre-SOC engineer, working on binutils SVP64 assembler - ghostmansd@gmail.com
    \item Jacob Lifshay - Libre-SOC engineer, CPU arch and verification - programmerjake@gmail.com
    \item Cesar Strauss - Libre-SOC engineer, CPU arch and verification - cestrauss@gmail.com
    \item Andrey Miroshnikov - Libre-SOC engineer, assisting with documentation - andrey@technepisteme.xyz
\end{itemize}

\newpage
\subsection*{Executive Summary}
\hypertarget{svux2fexecutive_summary}{}
\input{tex_out/executive_summary.tex}
 
\newpage
\begin{landscape}
\addcontentsline{toc}{chapter}{Comparison Table} \markboth{INTRODUCTION}{}
\hypertarget{svux2fcomparison_table}{}
{
\fontsize{6}{8}\selectfont
\input{tex_out/comparison_table.tex}
}
\end{landscape}

\part{Scalable Vectors Primer}
\input{svp64-primer/acronyms}
%\chapter*{Executive Summary}
\include{svp64-primer/summary}
\bibliography{svp64-primer/references}
\bibliographystyle{ieeetr}

\tableofcontents

% Part II
\part{Scalable Vectors for the Power ISA}


\chapter{Fields and Forms}
\hypertarget{svux2ffields}{}
\input{tex_out/fields.tex}
\chapter{Scalable Vectors for the Power ISA}
\hypertarget{svux2fscalvecpowisa}{}
\hypertarget{SVux7csv}{}
\input{tex_out/sv.tex}
\chapter{Other Vector ISAs}\hypertarget{svux2fvector_isa_comparison}{}
\input{tex_out/vector_isas.tex}
\chapter{Overview}\hypertarget{svux2foverview}{}
\input{tex_out/overview.tex}
\chapter{Compliancy Levels}\hypertarget{svux2fcompliancy_levels}{}
\input{tex_out/compliancy_levels.tex}
\chapter{SVP64}\hypertarget{svux2fsvp64}{}
\input{tex_out/svp64.tex}
\chapter{SPRs}\hypertarget{svux2fsprs}{}
\input{tex_out/sprs.tex}
\chapter{Arithmetic Mode}\hypertarget{svux2fnormal}{}
\input{tex_out/normal.tex}
\chapter{Load/Store Mode}\hypertarget{svux2fldst}{}
\input{tex_out/ldst.tex}
\chapter{Condition Register Fields Mode}\hypertarget{svux2fcr_ops}{}
\input{tex_out/cr_ops.tex}
\chapter{Branch Mode}\hypertarget{svux2fbranches}{}
\input{tex_out/branches.tex}
\chapter{setvl instruction}\hypertarget{svux2fsetvl}{}
\input{tex_out/setvl.tex}
\chapter{svstep instruction}\hypertarget{svux2fsvstep}{}
\input{tex_out/svstep.tex}
\chapter{REMAP subsystem}\hypertarget{svux2fremap}{}
\input{tex_out/remap.tex}
\chapter{Swizzle Move}\hypertarget{svux2fmv.swizzle}{}
\input{tex_out/mv_swizzle.tex}
\chapter{Pack / Unpack}\hypertarget{svux2fmv.vec}{}
\input{tex_out/mv_vec.tex}

\begin{appendices}
\chapter{SVP64 Appendix}\hypertarget{svp64ux2fappendix}{}
\hypertarget{svux2fsvp64ux2fappendix}{}
\input{tex_out/svp64_appendix.tex}
\chapter{SVP64 Quirks}\hypertarget{svux2fsvp64_quirks}{}
\input{tex_out/svp64_quirks.tex}
\chapter{REMAP algorithms}\hypertarget{svux2fremapux2fappendix}{}
\input{tex_out/remap_appendix.tex}
\chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
\input{tex_out/pseudocode_simplev.tex}
\chapter{Simple-V Analysis}\hypertarget{svux2fsv_analysis}{}
\input{tex_out/sv_analysis.tex}

\chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
\begin{landscape}
{
\fontsize{7}{9}\selectfont
\input{tex_out/opcode_regs_deduped.tex}
}
\end{landscape}

\end{appendices}

% Part III
\part{Scalar Instructions}

\chapter*{Preamble}{}

As explained in the Simple-V introduction
these are all intentionally and specifically Scalar instructions.
Each section is free-standing, has no connection, dependence or
relationship to any other section, including no direct critical dependence
either way on Simple-V.
They have with almost no exceptions been specifically crafted to
have a justification for their inclusion in the Power ISA as Scalar
instructions purely on their own merit.

\begin{itemize}
	\item The biginteger multiply-and-add instruction is similar
	to Intel's mulx in that it produces a pair of results.
	\item Javascript(tm) rounding is present in ARM as fjcvtzs
	and would save an astounding 35 instructions with 5 branches.
	\item Whilst there exist CR bit manipulation and copying
	instructions there are no CR Field manipulation instructions,
	putting pressure on GPRs if several CR fits need to be analysed.
	\item one single instruction, bmask, is proposed that covers
	the whole of x86 BMI1 and AMD TBM, combined, and provides more.
\end{itemize}

All of these have nothing to do with Simple-V at all: they make
the Power ISA better at modern general-purpose compute, bringing
it up-to-date.

That said: by a wonderful coincidence, should they be included, then
Simple-V's capabilities increase significantly. For example the CRweird
instructions combined with the bitmanip instructions, alongside 
Vectorised Rc=1 turn CR Fields into
extremely powerful Predicate masks. bmask not only
covers the BMI and TBM instructions of Intel and AMD it also
includes the RVV set-before-first and set-after-first instructions.

The clean and clear separation between Vectorisation Prefix and Scalar
Suffix is what makes it possible for both Scalar-only and Scalable-Vectors
to benefit.  It also makes proposal much easier, as there is no
inter-dependence.

It is however important to note that the rationale for these instructions
comes from a more general-purpose modern computing paradigm that is
outside of IBM's much more focussed and specialist traditional customer
base. We deeply respect IBM's curator role of the Power ISA of the past 25
years as much as we appreciate their courage in transferring that role
to the OpenPOWER Foundation ISA Working Group.

\chapter{SV Vector-assist Scalar ops}\hypertarget{svux2fvector_ops}{}
\input{tex_out/vector_ops.tex}
\chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
\hypertarget{cr_int_predication}{}
\input{tex_out/cr_int_predication.tex}
\chapter{Bitmanip ops}\hypertarget{svux2fbitmanip}{}
\input{tex_out/bitmanip.tex}
\chapter{FP/Int Conversion ops}\hypertarget{svux2fint_fp_mv}{}
\input{tex_out/int_fp_mv.tex}
\chapter{FP Class ops}\hypertarget{svux2ffclass}{}
\input{tex_out/fclass.tex}
\chapter{Audio and Video Opcodes}\hypertarget{svux2fav_opcodes}{}
\hypertarget{av_opcodes}{}
\input{tex_out/av_opcodes.tex}
\chapter{Big Integer}\hypertarget{svux2fbiginteger}{}
\input{tex_out/big_integer.tex}
\chapter{Transcendentals}\hypertarget{transcendentals}{}
\input{tex_out/transcendentals.tex}
%\chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
%\input{tex_out/atomics.tex}

\begin{appendices}
\chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
\input{tex_out/big_integer_analysis.tex}
\chapter{Bitmanip pseudocode}\hypertarget{svux2fpseudocode_bitmanip}{}
\input{tex_out/pseudocode_bitmanip.tex}
\chapter{Floating Point pseudocode}\hypertarget{isaux2fsvfparith}{}
\input{tex_out/pseudocode_svfparith.tex}
\chapter{Fixed Point pseudocode}
\hypertarget{isaux2fsvfixedarith}{}
\input{tex_out/pseudocode_svfixedarith.tex}
\end{appendices}

% Part IV
\part{Scalar Power ISA pseudocode}
\backmatter % temporary fix for too many appenfices
%\setcounter{chapter}{0}
%\renewcommand{\thechapter}{\Alph{chapter}}

\chapter*{Preamble}
\addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}

This section contains updated pseudocode from the Power ISA Specification
v3.0B to be executable.  Several bugfixes in Power ISA v3.0B have been
found and reported as a direct result due to actually running the
pseudocode as executable code in a Simulator.
A Formal Correctness Proof Research Paper written by Boris
Shingarov.

Additionally, with SVP64 performing element-width over-rides it is the
\textit{Scalar} pseudocode that needs adapting to variable-length
(\textbf{XLEN}).  Maintaining duplicate identical copies in every
respect \textit{except} for an XLEN as part of the Simple-V Specification
is completely pointless and a waste of time: the updates to include
XLEN need to be part
of the Scalar Power ISA Specification.  This has the added benefit
that it makes life much easier for 32-bit implementors, and has an
additional benefit of making it possible for the Scalar Power ISA
to extend to 128-bit in future (like RV128).

\begin{appendices}
\chapter{Binary Coded Decimal pseudocode}
\hypertarget{svux2fpseudocode_bcd}{}
\input{tex_out/pseudocode_bcd.tex}
\chapter{Branch pseudocode}
\hypertarget{openpowerux2fisaux2fbranch}{}
\hypertarget{svux2fpseudocode_branch}{}
\input{tex_out/pseudocode_branch.tex}
\chapter{Fixed Point Compare pseudocode}
\hypertarget{svux2fpseudocode_comparefixed}{}
\input{tex_out/pseudocode_comparefixed.tex}
\chapter{Condition Register pseudocode}
\hypertarget{svux2fpseudocode_condition}{}
\input{tex_out/pseudocode_condition.tex}

\chapter{Fixed Point Arithmetic pseudocode}
\hypertarget{svux2fpseudocode_fixedarith}{}
\input{tex_out/pseudocode_fixedarith.tex}
\chapter{Fixed Point Load pseudocode}
\hypertarget{svux2fpseudocode_fixedload}{}
\input{tex_out/pseudocode_fixedload.tex}
\chapter{Fixed Point Logical pseudocode}
\hypertarget{svux2fpseudocode_fixedlogical}{}
\input{tex_out/pseudocode_fixedlogical.tex}
\chapter{Fixed Point Rotate pseudocode}
\hypertarget{svux2fpseudocode_fixedshift}{}
\input{tex_out/pseudocode_fixedshift.tex}

\chapter{Fixed Point Store pseudocode}
\hypertarget{svux2fpseudocode_fixedstore}{}
\input{tex_out/pseudocode_fixedstore.tex}
\chapter{Fixed Point Trap pseudocode}
\hypertarget{svux2fpseudocode_fixedtrap}{}
\input{tex_out/pseudocode_fixedtrap.tex}
\chapter{Special Purpose Register pseudocode}
\hypertarget{svux2fpseudocode_sprset}{}
\input{tex_out/pseudocode_sprset.tex}
\chapter{String Load/Store pseudocode}
\hypertarget{svux2fpseudocode_stringldst}{}
\input{tex_out/pseudocode_stringldst.tex}
\chapter{System Call pseudocode}
\hypertarget{svux2fpseudocode_system}{}
\input{tex_out/pseudocode_system.tex}

\chapter{Floating Point Load pseudocode}
\hypertarget{svux2fpseudocode_fpload}{}
\input{tex_out/pseudocode_fpload.tex}
\chapter{Floating Point Store pseudocode}
\hypertarget{svux2fpseudocode_fpstore}{}
\input{tex_out/pseudocode_fpstore.tex}
\chapter{Floating Point Move pseudocode}
\hypertarget{svux2fpseudocode_fpmove}{}
\input{tex_out/pseudocode_fpmove.tex}
\chapter{Floating Point Arithmetic pseudocode}
\hypertarget{svux2fpseudocode_fparith}{}
\input{tex_out/pseudocode_fparith.tex}
\chapter{Floating Point Integer Conversion pseudocode}
\hypertarget{svux2fpseudocode_fpcvt}{}
\input{tex_out/pseudocode_fpcvt.tex}

\end{appendices}




\end{document}
