# Demo of encoding that's backward-compatible with PowerISA v3.1 in both LE and BE mode ## Assumed instruction encodings for this encoding demo Bits numbered using MSB0. Ranges are inclusive. ### Small Register Field Encoding | Encoding | Register | |----------|----------| | 0 | R3 | | 1 | R4 | | 2 | R5 | | 3 | R6 | | 4 | R28 | | 5 | R29 | | 6 | R30 | | 7 | R31 | ### Instruction Fields | Name | Range | Standard | Description | |------|--------------|---------------|-----------------------------------------------------| | PO | 0:5 | PowerISA v3.0 | Primary Opcode | | XO | 21:30 | PowerISA v3.0 | Extended Opcode | | SCM | 15 | New | Swap between Compressed & standard Mode | | SCMT | 0 | New | Swap between Compressed & standard Mode Temporarily | | SI | 16:31 | PowerISA v3.0 | Signed Immediate | | si0 | prefix 14:31 | PowerISA v3.1 | upper 18 bits Signed Immediate | | si1 | suffix 16:31 | PowerISA v3.1 | lower 16 bits Signed Immediate | | SO | 6:8 | New | Small Opcode for 16-bit instructions | | SOH | 1:5 | New | Small Opcode High bits for 16-bit instructions | | SRS | 12:14 | New | Small Source Register for 16-bit instructions | | SRT | 9:11 | New | Small Target Register for 16-bit instructions | ### Mnemonic Prefixes | Prefix | Mode | Next Mode | Next Next Mode | Instruction Width | Example | Comment | |------------|------------|------------|----------------|-------------------|-------------------------|------------------------------------------------| | _\_ | Standard | Standard | - | 32-bit | `addi R3, R3, 0x15` | Defined by PowerISA v3.0 | | `p` | Standard | Standard | - | 64-bit | `paddi R3, R3, 0x12345` | Defined by PowerISA v3.1 | | `x.` | Standard | Standard | - | 48-bit | `x.placeholder` | `x` means heXa-byte | | `h.` | Standard | Standard | - | 16-bit | `h.add R3, R4` | `h` means Half-word | | `hs.` | Standard | Compressed | - | 16-bit | `hs.add R3, R4` | `hs` means Half-word & Swap mode | | `c.` | Compressed | Compressed | - | 16-bit | `c.addi R3, R4, 0x5` | `c` means Compressed | | `cs.` | Compressed | Standard | - | 16-bit | `cs.add R3, R4` | `cs` means Compressed & Swap mode | | `cst.` | Compressed | Standard | Compressed | 16-bit | `cst.add R3, R4` | `cst` means Compressed & Swap mode Temporarily | ### Standard Mode #### Standard Mode 32-bit Instructions (PowerISA v3.0) | Mnemonic | PO (0:5) | RT (6:10) | RA (11:15) | SI (16:31) | Operation | |----------------------|----------|-----------|------------|------------|--------------------------------| | `addi RT, RA, immed` | 14 | RT | RA | SI | RT <- (RA|0) + EXTS64(SI) | #### Standard Mode 64-bit Instructions (PowerISA v3.1) Note that bit numbering goes from 0 to 31 in the prefix, then 0 to 31 in the suffix -- following the numbering in the PowerISA v3.1 spec. | Field | Value | |-------------|------------------------------------------------| | Mnemonic | `paddi RT, RA, immed` | | PO (0:5) | 1 | | (6:7) | 2 | | (8) | 0 | | (9:10) | // | | R (11) | 0 | | (12:13) | // | | si0 (14:31) | si0 | | PO (0:5) | 14 | | RT (6:10) | RT | | RA (11:15) | RA | | si1 (16:31) | si1 | | Operation | RT <- (RA|0) + EXTS64(si0||si1) | #### Standard Mode 16-bit Instructions (New) | Mnemonic | PO (0:5) | SO (6:8) | SRT (9:11) | SRS (12:14) | SCM (15) | Operation | |---------------|----------|----------|------------|-------------|----------|---------------------------------------------| | h.add RT, RS | 5 | 0 | RT | RS | 0 | RT <- RT + RS | | hs.add RT, RS | 5 | 0 | RT | RS | 1 | RT <- RT + RS
Swap to Compressed Mode | #### Standard Mode 48-bit Instructions (New; Placeholder) | Mnemonic | PO (0:5) | placeholder (6:20) | XO (21:30) | placeholder (31:47) | Operation | |---------------|----------|--------------------|------------|---------------------|-------------| | x.placeholder | 0 | placeholder | 1 | placeholder | placeholder | ### Compressed Mode #### Compressed Mode 16-bit Instructions (New) | Mnemonic | SCMT (0) | SOH (1:5) | SO (6:8) | SRT (9:11) | SRS (12:14) | SCM (15) | Operation | |----------------|----------|-----------|----------|------------|-------------|----------|-------------------------------------------------------| | c.add RT, RS | 0 | 1 | 0 | RT | RS | 0 | RT <- RT + RS | | cs.add RT, RS | 0 | 1 | 0 | RT | RS | 1 | RT <- RT + RS
Swap to Standard Mode | | cst.add RT, RS | 1 | 1 | 0 | RT | RS | 1 | RT <- RT + RS
Swap to Standard Mode Temporarily | ### Assembler bash script [[demo_assembler.sh]] ## Big-Endian Machine Code | Address | Byte | PC | Mode | Instruction | |---------|------------------------------------------|----------------------------------------------|-----------------------------------------------------|---------------------------------------------------------------| | 0x1000 |
0x38
|
0x1000+0
|
Standard
|
addi r3, r4, 5
| | 0x1001 |
0x64
|
0x1000+1
|
Standard
|
addi r3, r4, 5
| | 0x1002 |
0x00
|
0x1000+2
|
Standard
|
addi r3, r4, 5
| | 0x1003 |
0x05
|
0x1000+3
|
Standard
|
addi r3, r4, 5
| | 0x1004 |
0x06
|
0x1004+0
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x1005 |
0x00
|
0x1004+1
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x1006 |
0xDE
|
0x1004+2
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x1007 |
0xAD
|
0x1004+3
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x1008 |
0x38
|
0x1004+4
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x1009 |
0x65
|
0x1004+5
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x100A |
0xBE
|
0x1004+6
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x100B |
0xEF
|
0x1004+7
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x100C |
0x00
|
0x100C+0
|
Standard
|
x.placeholder
| | 0x100D |
0x00
|
0x100C+1
|
Standard
|
x.placeholder
| | 0x100E |
0x00
|
0x100C+2
|
Standard
|
x.placeholder
| | 0x100F |
0x02
|
0x100C+3
|
Standard
|
x.placeholder
| | 0x1010 |
0x00
|
0x100C+4
|
Standard
|
x.placeholder
| | 0x1011 |
0x00
|
0x100C+5
|
Standard
|
x.placeholder
| | 0x1012 |
0x38
|
0x1012+0
|
Standard
|
addi r3, r4, 5
| | 0x1013 |
0x64
|
0x1012+1
|
Standard
|
addi r3, r4, 5
| | 0x1014 |
0x00
|
0x1012+2
|
Standard
|
addi r3, r4, 5
| | 0x1015 |
0x05
|
0x1012+3
|
Standard
|
addi r3, r4, 5
| | 0x1016 |
0x06
|
0x1016+0
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x1017 |
0x00
|
0x1016+1
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x1018 |
0x89
|
0x1016+2
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x1019 |
0xAB
|
0x1016+3
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x101A |
0x38
|
0x1016+4
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x101B |
0x65
|
0x1016+5
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x101C |
0xCD
|
0x1016+6
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x101D |
0xEF
|
0x1016+7
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x101E |
0x00
|
0x101E+0
|
Standard
|
x.placeholder
| | 0x101F |
0x00
|
0x101E+1
|
Standard
|
x.placeholder
| | 0x1020 |
0x00
|
0x101E+2
|
Standard
|
x.placeholder
| | 0x1021 |
0x02
|
0x101E+3
|
Standard
|
x.placeholder
| | 0x1022 |
0x00
|
0x101E+4
|
Standard
|
x.placeholder
| | 0x1023 |
0x00
|
0x101E+5
|
Standard
|
x.placeholder
| | 0x1024 |
0x14
|
0x1024+0
|
Standard
|
h.add r3, r4
| | 0x1025 |
0x02
|
0x1024+1
|
Standard
|
h.add r3, r4
| | 0x1026 |
0x38
|
0x1026+0
|
Standard
|
addi r3, r6, 7
| | 0x1027 |
0x66
|
0x1026+1
|
Standard
|
addi r3, r6, 7
| | 0x1028 |
0x00
|
0x1026+2
|
Standard
|
addi r3, r6, 7
| | 0x1029 |
0x07
|
0x1026+3
|
Standard
|
addi r3, r6, 7
| | 0x102A |
0x14
|
0x102A+0
|
Standard
|
hs.add r3, r31
| | 0x102B |
0x0F
|
0x102A+1
|
Standard
|
hs.add r3, r31
| | 0x102C |
0x04
|
0x102C+0
|
Compressed
|
c.add r3, r30
| | 0x102D |
0x0C
|
0x102C+1
|
Compressed
|
c.add r3, r30
| | 0x102E |
0x84
|
0x102E+0
|
Compressed
|
cst.add r3, r29
| | 0x102F |
0x0B
|
0x102E+1
|
Compressed
|
cst.add r3, r29
| | 0x1030 |
0x06
|
0x1030+0
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1031 |
0x00
|
0x1030+1
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1032 |
0x12
|
0x1030+2
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1033 |
0x34
|
0x1030+3
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1034 |
0x38
|
0x1030+4
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1035 |
0x7F
|
0x1030+5
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1036 |
0x56
|
0x1030+6
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1037 |
0x78
|
0x1030+7
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1038 |
0x04
|
0x1038+0
|
Compressed
|
c.add r3, r5
| | 0x1039 |
0x04
|
0x1038+1
|
Compressed
|
c.add r3, r5
| | 0x103A |
0x04
|
0x103A+0
|
Compressed
|
c.add r3, r3
| | 0x103B |
0x00
|
0x103A+1
|
Compressed
|
c.add r3, r3
| | 0x103C |
0x04
|
0x103C+0
|
Compressed
|
cs.add r3, r6
| | 0x103D |
0x07
|
0x103C+1
|
Compressed
|
cs.add r3, r6
| | 0x103E |
0x38
|
0x103E+0
|
Standard
|
addi r3, r3, 0x23
| | 0x103F |
0x63
|
0x103E+1
|
Standard
|
addi r3, r3, 0x23
| | 0x1040 |
0x00
|
0x103E+2
|
Standard
|
addi r3, r3, 0x23
| | 0x1041 |
0x23
|
0x103E+3
|
Standard
|
addi r3, r3, 0x23
| | 0x1042 |
0x38
|
0x1042+0
|
Standard
|
addi r3, r10, 0xA
| | 0x1043 |
0x6A
|
0x1042+1
|
Standard
|
addi r3, r10, 0xA
| | 0x1044 |
0x00
|
0x1042+2
|
Standard
|
addi r3, r10, 0xA
| | 0x1045 |
0x0A
|
0x1042+3
|
Standard
|
addi r3, r10, 0xA
| | 0x1046 |
0x14
|
0x1046+0
|
Standard
|
hs.add r3, r5
| | 0x1047 |
0x05
|
0x1046+1
|
Standard
|
hs.add r3, r5
| | 0x1048 |
0x84
|
0x1048+0
|
Compressed
|
cst.add r3, r4
| | 0x1049 |
0x03
|
0x1048+1
|
Compressed
|
cst.add r3, r4
| | 0x104A |
0x14
|
0x104A+0
|
Std. Then Comp.
|
hs.add r3, r6
| | 0x104B |
0x07
|
0x104A+1
|
Std. Then Comp.
|
hs.add r3, r6
| | 0x104C |
0x84
|
0x104C+0
|
Compressed
|
cst.add r3, r28
| | 0x104D |
0x09
|
0x104C+1
|
Compressed
|
cst.add r3, r28
| | 0x104E |
0x14
|
0x104E+0
|
Std. Then Comp.
|
h.add r3, r29
| | 0x104F |
0x0A
|
0x104E+1
|
Std. Then Comp.
|
h.add r3, r29
| | 0x1050 |
0x84
|
0x1050+0
|
Compressed
|
cst.add r3, r30
| | 0x1051 |
0x0D
|
0x1050+1
|
Compressed
|
cst.add r3, r30
| | 0x1052 |
0x00
|
0x1052+0
|
Std. Then Comp.
|
x.placeholder
| | 0x1053 |
0x00
|
0x1052+1
|
Std. Then Comp.
|
x.placeholder
| | 0x1054 |
0x00
|
0x1052+2
|
Std. Then Comp.
|
x.placeholder
| | 0x1055 |
0x02
|
0x1052+3
|
Std. Then Comp.
|
x.placeholder
| | 0x1056 |
0x00
|
0x1052+4
|
Std. Then Comp.
|
x.placeholder
| | 0x1057 |
0x00
|
0x1052+5
|
Std. Then Comp.
|
x.placeholder
| | 0x1058 |
0x84
|
0x1058+0
|
Compressed
|
cst.add r3, r31
| | 0x1059 |
0x0F
|
0x1058+1
|
Compressed
|
cst.add r3, r31
| | 0x105A |
0x38
|
0x105A+0
|
Std. Then Comp.
|
addi r3, r15, 0xF
| | 0x105B |
0x6F
|
0x105A+1
|
Std. Then Comp.
|
addi r3, r15, 0xF
| | 0x105C |
0x00
|
0x105A+2
|
Std. Then Comp.
|
addi r3, r15, 0xF
| | 0x105D |
0x0F
|
0x105A+3
|
Std. Then Comp.
|
addi r3, r15, 0xF
| | 0x105E |
0x04
|
0x105E+0
|
Compressed
|
cs.add r3, r4
| | 0x105F |
0x03
|
0x105E+1
|
Compressed
|
cs.add r3, r4
| | 0x1060 |
0x38
|
0x1060+0
|
Standard
|
addi r3, r10, 0xF
| | 0x1061 |
0x6A
|
0x1060+1
|
Standard
|
addi r3, r10, 0xF
| | 0x1062 |
0x00
|
0x1060+2
|
Standard
|
addi r3, r10, 0xF
| | 0x1063 |
0x0F
|
0x1060+3
|
Standard
|
addi r3, r10, 0xF
| | 0x1064 |
0x38
|
0x1064+0
|
Standard
|
addi r3, r11, 0xF
| | 0x1065 |
0x6B
|
0x1064+1
|
Standard
|
addi r3, r11, 0xF
| | 0x1066 |
0x00
|
0x1064+2
|
Standard
|
addi r3, r11, 0xF
| | 0x1067 |
0x0F
|
0x1064+3
|
Standard
|
addi r3, r11, 0xF
| ## Little-Endian Machine Code | Address | Byte | PC | Mode | Instruction | |---------|------------------------------------------|----------------------------------------------|-----------------------------------------------------|---------------------------------------------------------------| | 0x1000 |
0x05
|
0x1000+3
|
Standard
|
addi r3, r4, 5
| | 0x1001 |
0x00
|
0x1000+2
|
Standard
|
addi r3, r4, 5
| | 0x1002 |
0x64
|
0x1000+1
|
Standard
|
addi r3, r4, 5
| | 0x1003 |
0x38
|
0x1000+0
|
Standard
|
addi r3, r4, 5
| | 0x1004 |
0xAD
|
0x1004+3
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x1005 |
0xDE
|
0x1004+2
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x1006 |
0x00
|
0x1004+1
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x1007 |
0x06
|
0x1004+0
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x1008 |
0xEF
|
0x1004+7
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x1009 |
0xBE
|
0x1004+6
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x100A |
0x65
|
0x1004+5
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x100B |
0x38
|
0x1004+4
|
Standard
|
paddi r3, r5, 0xDEADBEEF
| | 0x100C |
0x02
|
0x100C+3
|
Standard
|
x.placeholder
| | 0x100D |
0x00
|
0x100C+2
|
Standard
|
x.placeholder
| | 0x100E |
0x00
|
0x100C+1
|
Standard
|
x.placeholder
| | 0x100F |
0x00
|
0x100C+0
|
Standard
|
x.placeholder
| | 0x1010 |
0x64
|
0x1012+1
|
Standard
|
addi r3, r4, 5
| | 0x1011 |
0x38
|
0x1012+0
|
Standard
|
addi r3, r4, 5
| | 0x1012 |
0x00
|
0x100C+5
|
Standard
|
x.placeholder
| | 0x1013 |
0x00
|
0x100C+4
|
Standard
|
x.placeholder
| | 0x1014 |
0x00
|
0x1016+1
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x1015 |
0x06
|
0x1016+0
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x1016 |
0x05
|
0x1012+3
|
Standard
|
addi r3, r4, 5
| | 0x1017 |
0x00
|
0x1012+2
|
Standard
|
addi r3, r4, 5
| | 0x1018 |
0x65
|
0x1016+5
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x1019 |
0x38
|
0x1016+4
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x101A |
0xAB
|
0x1016+3
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x101B |
0x89
|
0x1016+2
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x101C |
0x00
|
0x101E+1
|
Standard
|
x.placeholder
| | 0x101D |
0x00
|
0x101E+0
|
Standard
|
x.placeholder
| | 0x101E |
0xEF
|
0x1016+7
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x101F |
0xCD
|
0x1016+6
|
Standard
|
paddi r3, r5, 0x89ABCDEF
| | 0x1020 |
0x00
|
0x101E+5
|
Standard
|
x.placeholder
| | 0x1021 |
0x00
|
0x101E+4
|
Standard
|
x.placeholder
| | 0x1022 |
0x02
|
0x101E+3
|
Standard
|
x.placeholder
| | 0x1023 |
0x00
|
0x101E+2
|
Standard
|
x.placeholder
| | 0x1024 |
0x66
|
0x1026+1
|
Standard
|
addi r3, r6, 7
| | 0x1025 |
0x38
|
0x1026+0
|
Standard
|
addi r3, r6, 7
| | 0x1026 |
0x02
|
0x1024+1
|
Standard
|
h.add r3, r4
| | 0x1027 |
0x14
|
0x1024+0
|
Standard
|
h.add r3, r4
| | 0x1028 |
0x0F
|
0x102A+1
|
Standard
|
hs.add r3, r31
| | 0x1029 |
0x14
|
0x102A+0
|
Standard
|
hs.add r3, r31
| | 0x102A |
0x07
|
0x1026+3
|
Standard
|
addi r3, r6, 7
| | 0x102B |
0x00
|
0x1026+2
|
Standard
|
addi r3, r6, 7
| | 0x102C |
0x0B
|
0x102E+1
|
Compressed
|
cst.add r3, r29
| | 0x102D |
0x84
|
0x102E+0
|
Compressed
|
cst.add r3, r29
| | 0x102E |
0x0C
|
0x102C+1
|
Compressed
|
c.add r3, r30
| | 0x102F |
0x04
|
0x102C+0
|
Compressed
|
c.add r3, r30
| | 0x1030 |
0x34
|
0x1030+3
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1031 |
0x12
|
0x1030+2
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1032 |
0x00
|
0x1030+1
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1033 |
0x06
|
0x1030+0
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1034 |
0x78
|
0x1030+7
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1035 |
0x56
|
0x1030+6
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1036 |
0x7F
|
0x1030+5
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1037 |
0x38
|
0x1030+4
|
Std. Then Comp.
|
paddi r3, r31, 0x12345678
| | 0x1038 |
0x00
|
0x103A+1
|
Compressed
|
c.add r3, r3
| | 0x1039 |
0x04
|
0x103A+0
|
Compressed
|
c.add r3, r3
| | 0x103A |
0x04
|
0x1038+1
|
Compressed
|
c.add r3, r5
| | 0x103B |
0x04
|
0x1038+0
|
Compressed
|
c.add r3, r5
| | 0x103C |
0x63
|
0x103E+1
|
Standard
|
addi r3, r3, 0x23
| | 0x103D |
0x38
|
0x103E+0
|
Standard
|
addi r3, r3, 0x23
| | 0x103E |
0x07
|
0x103C+1
|
Compressed
|
cs.add r3, r6
| | 0x103F |
0x04
|
0x103C+0
|
Compressed
|
cs.add r3, r6
| | 0x1040 |
0x6A
|
0x1042+1
|
Standard
|
addi r3, r10, 0xA
| | 0x1041 |
0x38
|
0x1042+0
|
Standard
|
addi r3, r10, 0xA
| | 0x1042 |
0x23
|
0x103E+3
|
Standard
|
addi r3, r3, 0x23
| | 0x1043 |
0x00
|
0x103E+2
|
Standard
|
addi r3, r3, 0x23
| | 0x1044 |
0x05
|
0x1046+1
|
Standard
|
hs.add r3, r5
| | 0x1045 |
0x14
|
0x1046+0
|
Standard
|
hs.add r3, r5
| | 0x1046 |
0x0A
|
0x1042+3
|
Standard
|
addi r3, r10, 0xA
| | 0x1047 |
0x00
|
0x1042+2
|
Standard
|
addi r3, r10, 0xA
| | 0x1048 |
0x07
|
0x104A+1
|
Std. Then Comp.
|
hs.add r3, r6
| | 0x1049 |
0x14
|
0x104A+0
|
Std. Then Comp.
|
hs.add r3, r6
| | 0x104A |
0x03
|
0x1048+1
|
Compressed
|
cst.add r3, r4
| | 0x104B |
0x84
|
0x1048+0
|
Compressed
|
cst.add r3, r4
| | 0x104C |
0x0A
|
0x104E+1
|
Std. Then Comp.
|
h.add r3, r29
| | 0x104D |
0x14
|
0x104E+0
|
Std. Then Comp.
|
h.add r3, r29
| | 0x104E |
0x09
|
0x104C+1
|
Compressed
|
cst.add r3, r28
| | 0x104F |
0x84
|
0x104C+0
|
Compressed
|
cst.add r3, r28
| | 0x1050 |
0x00
|
0x1052+1
|
Std. Then Comp.
|
x.placeholder
| | 0x1051 |
0x00
|
0x1052+0
|
Std. Then Comp.
|
x.placeholder
| | 0x1052 |
0x0D
|
0x1050+1
|
Compressed
|
cst.add r3, r30
| | 0x1053 |
0x84
|
0x1050+0
|
Compressed
|
cst.add r3, r30
| | 0x1054 |
0x00
|
0x1052+5
|
Std. Then Comp.
|
x.placeholder
| | 0x1055 |
0x00
|
0x1052+4
|
Std. Then Comp.
|
x.placeholder
| | 0x1056 |
0x02
|
0x1052+3
|
Std. Then Comp.
|
x.placeholder
| | 0x1057 |
0x00
|
0x1052+2
|
Std. Then Comp.
|
x.placeholder
| | 0x1058 |
0x6F
|
0x105A+1
|
Std. Then Comp.
|
addi r3, r15, 0xF
| | 0x1059 |
0x38
|
0x105A+0
|
Std. Then Comp.
|
addi r3, r15, 0xF
| | 0x105A |
0x0F
|
0x1058+1
|
Compressed
|
cst.add r3, r31
| | 0x105B |
0x84
|
0x1058+0
|
Compressed
|
cst.add r3, r31
| | 0x105C |
0x03
|
0x105E+1
|
Compressed
|
cs.add r3, r4
| | 0x105D |
0x04
|
0x105E+0
|
Compressed
|
cs.add r3, r4
| | 0x105E |
0x0F
|
0x105A+3
|
Std. Then Comp.
|
addi r3, r15, 0xF
| | 0x105F |
0x00
|
0x105A+2
|
Std. Then Comp.
|
addi r3, r15, 0xF
| | 0x1060 |
0x0F
|
0x1060+3
|
Standard
|
addi r3, r10, 0xF
| | 0x1061 |
0x00
|
0x1060+2
|
Standard
|
addi r3, r10, 0xF
| | 0x1062 |
0x6A
|
0x1060+1
|
Standard
|
addi r3, r10, 0xF
| | 0x1063 |
0x38
|
0x1060+0
|
Standard
|
addi r3, r10, 0xF
| | 0x1064 |
0x0F
|
0x1064+3
|
Standard
|
addi r3, r11, 0xF
| | 0x1065 |
0x00
|
0x1064+2
|
Standard
|
addi r3, r11, 0xF
| | 0x1066 |
0x6B
|
0x1064+1
|
Standard
|
addi r3, r11, 0xF
| | 0x1067 |
0x38
|
0x1064+0
|
Standard
|
addi r3, r11, 0xF
|