[[!tag standards]]

# Scalar OpenPOWER Audio and Video Opcodes

the fundamental principle of SV is a hardware for-loop. therefore the first (and in nearly 100% of cases only) place to put Vector operations is first and foremost in the *scalar* ISA.  However only by analysing those scalar opcodes *in* a SV Vectorization context does it become clear why they are needed and how they may be designed.

This page therefore has accompanying discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=230> for evolution of suitable opcodes.

Links

* <https://bugs.libre-soc.org/show_bug.cgi?id=915> add overflow to maxmin.
* <https://bugs.libre-soc.org/show_bug.cgi?id=863> add pseudocode etc.
* <https://bugs.libre-soc.org/show_bug.cgi?id=234> hardware implementation
* <https://bugs.libre-soc.org/show_bug.cgi?id=910> mins/maxs zero-option?
* <https://bugs.libre-soc.org/show_bug.cgi?id=1057> move all int/fp min/max to ls013
* [[vpu]]
* [[sv/int_fp_mv]]
* [[openpower/isa/av]] pseudocode
* [[av_opcodes/analysis]]
* TODO review HP 1994-6 PA-RISC MAX <https://en.m.wikipedia.org/wiki/Multimedia_Acceleration_eXtensions>
* <https://en.m.wikipedia.org/wiki/Sum_of_absolute_differences>
* List of MMX instructions <https://cs.fit.edu/~mmahoney/cse3101/mmx.html>

# Summary

In-advance, the summary of base scalar operations that need to be added is:

| instruction   | pseudocode               |
| ------------  | ------------------------      |
| average-add.  | result = (src1 + src2 + 1) >> 1 |
| abs-diff      | result = abs (src1-src2) |
| abs-accumulate| result += abs (src1-src2) |
| (un)signed min| result = (src1 < src2) ? src1 : src2 [[ls013]] |
| (un)signed max| result = (src1 > src2) ? src1 : src2 [[ls013]]  |
| bitwise sel   | (a ? b : c) - use [[sv/bitmanip]] ternary |
| int/fp move   | covered by REMAP and Pack/Unpack |

Implemented at the [[openpower/isa/av]] pseudocode page.

All other capabilities (saturate in particular) are achieved with [[sv/svp64]] modes and swizzle.  Note that minmax and ternary are added in bitmanip.

# Instructions

## Average Add

X-Form

* avgadd  RT,RA,RB (Rc=0)
* avgadd. RT,RA,RB (Rc=1)

Pseudo-code:

    a <- [0] * (XLEN+1)
    b <- [0] * (XLEN+1)
    a[1:XLEN] <- (RA)
    b[1:XLEN] <- (RB)
    r <- (a + b + 1)
    RT <- r[0:XLEN-1]

Special Registers Altered:

    CR0                     (if Rc=1)

## Absolute Signed Difference

X-Form

* absds  RT,RA,RB (Rc=0)
* absds. RT,RA,RB (Rc=1)

Pseudo-code:

    if (RA) < (RB) then RT <- ¬(RA) + (RB) + 1
    else                RT <- ¬(RB) + (RA) + 1

Special Registers Altered:

    CR0                     (if Rc=1)

## Absolute Unsigned Difference

X-Form

* absdu  RT,RA,RB (Rc=0)
* absdu. RT,RA,RB (Rc=1)

Pseudo-code:

    if (RA) <u (RB) then RT <- ¬(RA) + (RB) + 1
    else                RT <- ¬(RB) + (RA) + 1

Special Registers Altered:

    CR0                     (if Rc=1)

## Absolute Accumulate Unsigned Difference

X-Form

* absdacu  RT,RA,RB (Rc=0)
* absdacu. RT,RA,RB (Rc=1)

Pseudo-code:

    if (RA) <u (RB) then r <- ¬(RA) + (RB) + 1
    else                 r <- ¬(RB) + (RA) + 1
    RT <- (RT) + r

Special Registers Altered:

    CR0                     (if Rc=1)

## Absolute Accumulate Signed Difference

X-Form

* absdacs  RT,RA,RB (Rc=0)
* absdacs. RT,RA,RB (Rc=1)

Pseudo-code:

    if (RA) < (RB) then r <- ¬(RA) + (RB) + 1
    else                r <- ¬(RB) + (RA) + 1
    RT <- (RT) + r

Special Registers Altered:

    CR0                     (if Rc=1)