# Data-dependent fail-first on CR operations

Data-dependent SVP64 Vectorised Operations involving the creation or
modification of a CR require an extra two bits, which are not available
in the compact space of the `MODE` Field. With the concept of element
width overrides being meaningless for CR Fields it is possible to use the
`ELWIDTH` field for extra fields.

Condition Register based operations such as `mfcr` and `crand` can thus
be made more flexible.  However the rules that apply in this section
also apply to future CR-based instructions.  Note that these rules and
the alternative mapping **only** applies to instructions that **only**
reference a CR Field or CR bit as the sole exclusive result. This section
**does not** apply to instructions which primarily produce arithmetic
results that also produce a CR Field (such as when Rc=1).

SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:

| 4 | 5 | 19-20 |  21 | 22   23 |  description     |
| - | - | ----- | --- |---------|----------------- |
|dz |VLi| 01    | inv |  CR-bit | normal mode      |
|sz |VLi| 01    | inv |  dz Rc1 | VLSET mode       |

Fields:

There are two primary different types of CR operations:

* Those which have a 3-bit operand field (referring to a CR Field)
* Those which have a 5-bit operand (referring to a bit within the
   whole 32-bit CR)

Examining these two as has already been done it is observed that the
difference may be considered to be that the 5-bit variant provides
additional information about which CR Field bit (EQ, GE, LT, SO) is to
be operated on by the instruction.

Thus, logically, we may set the following rule:

* When a 5-bit CR Result field is used in an instruction, the
  `inv, VLi and RC1` variant of Data-Dependent Fail-First
  must be used. i.e. the bit of the CR field to be tested is
  the one that has just been modified by the operation.
* When a 3-bit CR Result field is used the `inv CRbit` variant
  must be used in order to select which CR Field bit shall
  be tested (EQ, LE, GE, SO)

The reason why the 3-bit CR variant needs the additional CR-bit
field should be obvious from the fact that the 3-bit CR Field
from the base Power ISA v3.0B operation clearly does not contain
and is missing the two CR Field Selector bits. Thus, these two
bits (to select EQ, LE, GE or SO) must be provided in another
way.

Examples of the former type:

* crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
  to be tested against `inv` is the one selected by `BT`
* mcrf. This has only 3-bit (BF, BFA). In order to select the
  bit to be tested, the alternative FFirst encoding must be used.

This limits sv.mcrf in that it may not use the `VLi` (VL inclusive)
Mode. This is unfortunste but unavoidable due to encoding pressure
on SVP64.