# Example Dependency Matrix Layouts

# Scalar with Vector "Lanes"

See <https://bugs.libre-soc.org/show_bug.cgi?id=213#c83>

| FU-REGS -| r0 | r1 | r2 | r3 | r4 | r5 | r6 | r7 |  FU-FU | L0A0 | L1A0 | L2A0 | L3A0 | L0A1 | L1A2 | L2A1 | L3A1 | SA1 | SA2 | SL1 | SL2 |
|----------|----|----|----|----|----|----|----|----|--------|------|------|----- |------|------|------|------|------|-----|-----|-----|-----|
|V\_L0\_ALU0| y  |    |    |    |  y |    |    |    |  ->    | y    |      |      |      | y    |      |      |      | ?   | ?   | ?   | ?   |
|V\_L1\_ALU0|    | y  |    |    |    |  y |    |    |  ->    |      |  y   |      |      |      | y    |      |      | ?   | ?   | ?   | ?   |
|V\_L2\_ALU0|    |    | y  |    |    |    | y  |    |  ->    |      |      | y    |      |      |      | y    |      | ?   | ?   | ?   | ?   |
|V\_L3\_ALU0|    |    |    | y  |    |    |    | y  |  ->    |      |      |      | y    |      |      |      | y    | ?   | ?   | ?   | ?   |
|V\_L0\_ALU1| y  |    |    |    |  y |    |    |    |  ->    | y    |      |      |      | y    |      |      |      | ?   | ?   | ?   | ?   |
|V\_L1\_ALU1|    | y  |    |    |    |  y |    |    |  ->    |      |  y   |      |      |      | y    |      |      | ?   | ?   | ?   | ?   |
|V\_L2\_ALU1|    |    | y  |    |    |    | y  |    |  ->    |      |      | y    |      |      |      | y    |      | ?   | ?   | ?   | ?   |
|V\_L3\_ALU1|    |    |    | y  |    |    |    | y  |  ->    |      |      |      | y    |      |      |      | y    | ?   | ?   | ?   | ?   |
|S\_ALU1    | y  | y  | y  | y  | y  | y  | y  | y  |  ->    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | y   | y   | y   | y   |
|S\_ALU2    | y  | y  | y  | y  | y  | y  | y  | y  |  ->    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | y   | y   | y   | y   |
|S\_LOGIC1  | y  | y  | y  | y  | y  | y  | y  | y  |  ->    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | y   | y   | y   | y   |
|S\_LOGIC2  | y  | y  | y  | y  | y  | y  | y  | y  |  ->    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | ?    | y   | y   | y   | y   |

Register allocation associated with this DM layout: Vectors may *only* be allocated to Vector FPs if RA%4 == RB%4
== RT%4 and all reg numbers are over 32.  otherwise they are allocated
to *scalar* FUs which has significantly less computational resources
but far greater crossbar routing.  This allows 4R1W regfiles to be used where normally ultra-costly 12R10W would be required.